AD5422 register read-back bit-shifted wth 5.6MHz clock

When I read back a register value from the AD5422 using the EVAL-CN0233-50PZ development kit, the value I get is wrong, appearing to be right shifted by a single bit.  This goes away if I lower my spi clock speed from 5.6 to 2.8MHz.  Would like to understand the root of this issue.  

Logic screen shots are attached.  I am expecting bit 12 to be logic high as per the figure labelled "spi okay.png".  You can observe in "spi bad.png" that the device output is slightly shifted so the clock rising edge is unable to catch it.

Thanks

attachments.zip
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  • 0
    •  Analog Employees 
    on Jul 2, 2018 11:16 AM

    Hi Eugene,

    As I understand, the ADuM3471 is only delaying the clock edges by the propagation delay, it doesn't reduce the clock speed. What happens is that there is a delay going into the ADuM3471 for the clock and then another delay from SDO going into the PMOD.

    This delays could easily be ~100ns which is already more than half of your period at 5.6MHz.

    If you measure at the test points between ADuM3471 and AD5422, there should be no delay on the SDO signal with respect to the clock.

    Best regards,

    Rainier

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  • 0
    •  Analog Employees 
    on Jul 2, 2018 11:16 AM

    Hi Eugene,

    As I understand, the ADuM3471 is only delaying the clock edges by the propagation delay, it doesn't reduce the clock speed. What happens is that there is a delay going into the ADuM3471 for the clock and then another delay from SDO going into the PMOD.

    This delays could easily be ~100ns which is already more than half of your period at 5.6MHz.

    If you measure at the test points between ADuM3471 and AD5422, there should be no delay on the SDO signal with respect to the clock.

    Best regards,

    Rainier

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