CN0301: Universal LVDT Signal Conditioning Circuit

Hi,Brandon!

Question 1

In the note

"The EVAL-CN0301-SDPZ evaluation board can be configured

to have one master oscillator between two LVDTs by populating

Jumper JP1 to Jumper JP3 with a shorting jumper and leaving

JP4 unpopulated."

why not populate JP1 , JP2 , JP4 and leaving JP3 unpopulated?

.

Question 2

In the schematic.

What's the purpose on the C16 and C18? They don't be showed in the AD698 datasheet.

Thanks!

              -dexter

Hi Dexter,

It appears you have found a mistake in the Circuit Note!

The statement should read:

"The EVAL-CN0301-SDPZ evaluation board can be configured

to have one master oscillator between two LVDTs by populating

Jumper JP1, JP2, and JP4 with a shorting jumper and leaving

JP3 unpopulated."

JP1 will short the inputs of C12, causing the clock to be driven by the Master device.

Shorting JP2 and JP4 with JP3 will allow the excitation from the Master to drive the level of the excitation of the Slave.

Best Regards,

James

Hi Dexter,

Thanks for finding that error in the circuit note, I will start the update process within ADI for that.

James,

Can you comment on Dexter's second question about C16 and C18?

Cheers,

Brandon

Hi Brandon,

Thanks for pointing out that I forgot to address Dexter's other question.

Hi Dexter,

The other capacitor is there to provide extra filtering.  It's not absolutely necessary.

Hi James,

Thanks for your help!

I have some  questions of the AD698 which bothered me for some time.Could we discuss in private ?