diff --git a/imx8mm-test.dtsi.orig b/imx8mm-test.dtsi
index 8067e4d..6a43567 100644
--- a/imx8mm-test.dtsi.orig
+++ b/imx8mm-test.dtsi
@@ -479,36 +479,44 @@
 		dsd-path = <1>;
 	};
 
-	ov5640_mipi: ov5640_mipi@3c {
-		compatible = "ovti,ov5640_mipi";
-		reg = <0x3c>;
-		status = "okay";
+	adv7280_mipi1: adv7280_mipi1@21 {
+        status = "okay";
+        compatible = "adi,adv7280-m";
+        reg = <0x21>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>;
+		pinctrl-0 = <&pinctrl_adv7280>;
+		powerdown-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 
+		reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "adv7280m_intrq";
+		adv,force-bt656-4 = <1>;
 		clocks = <&clk IMX8MM_CLK_CLKO1>;
 		clock-names = "csi_mclk";
 		assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
-		assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
-		assigned-clock-rates = <24000000>;
+        assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
+        assigned-clock-rates = <24000000>;
 		csi_id = <0>;
-		pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
-		mclk = <24000000>;
-		mclk_source = <0>;
-		port {
-			ov5640_mipi1_ep: endpoint {
-				remote-endpoint = <&mipi1_sensor_ep>;
-			};
+        mclk = <24000000>;
+        mclk_source = <0>;
+        port {
+            adv7280_mipi1_ep: endpoint {
+                remote-endpoint = <&mipi1_sensor_ep>;
+                clock-lanes = <1>;
+                data-lanes = <1>;
+            };
 		};
 	};
+	

 	};
 
 	
@@ -524,11 +532,13 @@
 	status = "okay";
 	port {
 		mipi1_sensor_ep: endpoint@1 {
-			remote-endpoint = <&ov5640_mipi1_ep>;
-			data-lanes = <2>;
+			remote-endpoint = <&adv7280_mipi1_ep>;
+			clock-lanes = <1>;
+			data-lanes = <1>;
 			csis-hs-settle = <13>;
 			csis-clk-settle = <2>;
 			csis-wclk;
+			bus-width = <1>;
 		};
 
 		csi1_mipi_ep: endpoint@2 {
@@ -784,15 +794,16 @@
 		fsl,pins = <
 			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x000
 			MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23       0x140  //int
-			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22       0x19 //rst
+			/*MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22       0x19 //rst*/
 			
 		>;
 	};
 
-    pinctrl_tch_ts: tchgrp {
+    pinctrl_adv7280: adv7280grp {
 			fsl,pins = < 
-			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19  //INT - P40 
-			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19  //RST - P38
+			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x140 /* PDN - P40 */
+			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /*  RST - P38*/
+			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x140 /* INT - P37 */
  		>;
  	};