DDS vs. PLL (round 2)

Blog Post created by JLKeip on May 4, 2017

20 years ago I used to listen to Paul Harvey on the radio from time to time. He was known for delving deeper into news stories than many other reporters would. I enjoyed that. I hadn't thought of him for a while, but as I was writing this, I could hear him and his signature phrase reverberating in my mind: 'And that... is the rest of the story'. So here is the rest of the story on the nuances of the advantages PLL typically has over DDS.


Power Consumption -

This amount of advantage for a PLL depends greatly on the frequency range you wish to synthesize. DDS has so much digital content that as you push up the sample rate, you significantly increase the power consumption, and you need higher sample rates to hit higher output frequencies. If your frequency set is sub 100 MHz or so, the power comparison gets quite competitive:  There exists a DDS with a top speed of 250 MSPS which consumes on the order of 50 mW (AD9913), so the gap between DDS and PLL here is not necessarily large. 

As process geometries shrink, the power gap will also shrink.


Price -

A price difference certainly exists. This gap can also shrink with geometries, but it can also shrink due to economies of scale.  PLLs are much more broadly used and drive much higher volumes, which helps cost structures.  If you are looking at a high volume application, and a DDS solution yields some advantage, you should expect to find some room for negotiation on the price point.


Broad Spectral Purity -

If you need a fractional N PLL, you'll see the gap shrink some, but it won't disappear entirely. An interesting note (exhibited below) regarding Programmable Modulus DDS's - if you utilize lower integer values in the denominator of your frequency equation, you will see the spurs significantly converge, greatly reducing the number of spurs. At its root, the dilemma is choosing between broad spectral purity and tuning resolution.


300 MHz output from a 2.1 GHz sample rate (Programmable Modulus)~299 MHz output from a 2.1 GHZ sample rate Non-Programmable Modulus DDS


Both of these plots use a DDS (AD9915 to be specific) running at 2.1 GSPS. The image on the left has the output set to 300 MHZ (exactly 1/7th the sample rate), whereas the image on the right is programmed to ~299 MHz. The reduction in the number of spurs is dramatic isn't it?


Ancillary Circuitry -

Not a whole lot to say here.  PLLs which rely on external VCOs (as many higher performance ones do), and those with external loop filters will also require a fair bit of board space beyond their footprint, but there isn't much to be done about the reconstruction filter component needs of the DDS.  I have seen a design or two which was able to use the raw output signal, but they are certainly in the minority.


Frequency Upconversion -

While upconversion is still not a word (no matter how hard I lobby), I still use it! There are two ways to bridge this gap.  One is to work with a Super Nyquist image frequency from the DDS rather than the fundamental.  Doing so reduces the output power of the signal, and it also makes the filter design more complex - a band pass filter must be designed as opposed to a low pass filter.

The other approach is to use a hybrid DDS/PLL based approach, which has the effect of mixing the advantages I have discussed:

Hopefully this gives you all the knowledge you need to make an informed decision on which route to go the next time you need to synthesize a signal for any need you come across.  I encourage you to ask questions here or in the DDS or RF-PLL forums of the Engineer Zone.   You'll also find sortable lists of our PLL and DDS portfolios at the analog.com website.