In order to fill the needs of many customers today the sample rate of our ADCs at ADI is getting pushed higher and higher. Customers desire to sample frequencies in the GHz range which comes with a stiff penalty of higher bandwidth in the digital data transmission. High frequency is needed but typically not high bandwidth. Generally about 100-200MHz at most is required but the operating frequency may be up at 1.5 GHz or higher. Here come DDCs to the rescue. With a DDC, input frequencies in the GHz range can be sampled by the ADC and then tuned and filtered by the DDC to select the 100-200MHz of required bandwidth. This allows the digital output bandwidth to be reduced to a manageable level resulting in less challenging layout and cheaper FPGAs. This all sounds great, but how does this DDC actually work. Take a look at my latest article on Analog Dialogue titled "What's Up with Digital Downconverters Part 1" to learn more. You can find it here: http://www.analog.com/library/analogdialogue/archives/50-07/digital-downconverters-part-1.html.
Stay tuned for the second part of the article coming up in Analog Dialogue in November of this year. I welcome any feedback and questions you may have.