I’m one of the applications engineer for the iCoupler devices here at Analog Devices.  I get lots of questions from customers about isolating SPI, so I thought it would be useful to write a blog post about an aspect that has been getting more attention as speed requirements increase.

Isolating SPI is very simple in the most cases.  The lines are all unidirectional and use standard digital logic levels for data, and no open collector outputs to support wire and connections.  As long as the speed is fairly modest, below about 5MHz clock rates, most digital isolators will do the job with no further fuss.  Unfortunately as the clock rate increases there is a catch that limits the speed.

Standard implementations of SPI use the clock signal, SCLKM, generated by the Master device to control all movement of data on the bus.  Data moves between the Master and Slave as if they were two interconnected shift registers.  The Master and Slave present data to the bus on one phase of the clock and read the data into their shift register on the opposite phase.  This system works fine as long as the round trip propagation delay through the bus is less than half of the clock period, because the data must be back to the master by the next clock edge, half a clock period later.

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Incorporating isolation into an SPI bus constrains the SCLKM rate because data from the Slave device must arrive at the Master before the next clock edge.  Since the minimum time required for this to happen is 2x the maximum propagation delay, this sets a maximum limit on the clock rate.

We usually recommend the ADuM1401C for this job since it has a guaranteed speed of 45 MHz with a maximum propagation delay of 32 ns.  When used to isolate SPI, the clock half period must be greater than 2 propagation delays, or a maximum SCLKM rate of 7.8MHz.  This is a severe limitation on the data rate compared to the maximum throughput of the digital isolator.  In fact, a digital isolator would need a maximum guaranteed propagation delay less than 5.5 ns to support 45 MHz SPI.

Luckily there is a straightforward solution to eliminate this bottleneck.  If the SCLKM signal is wrapped back through the coupler along with the data from the Slave device, the timing between the new signal, SCLKS, and the data is the same to within the propagation delay skew of the coupler.  SCLKS can be used to clock data back into the Master at rates which are again set by guaranteed data rate of the coupler.  After each transaction, the secondary buffer MREG2 is copied into MREG1  In this example, that raises the SPI clock rate to the full 45MHZ, a 5x improvement.  The cost of this solution is the additional coupler channel to wrap the Master clock signal and an extra input shift register in the master controller

The recommended iCoupler devices for SPI applications are the ADuM1401C and ADuM3441.  Data rates of up to 50 MHz can be achieved with these devices.

You can learn more about these devices on our website at: www.analog.com/icoupler.

If you have any questions or comments about this particular issue, feel free to add them below.

Anonymous
    •  Analog Employees 
    over 9 years ago in reply to stinf

    Hello Stinf

    Yes we have solutions that include power.  Please look at the ADuM540x or ADuM640x isoPower parts depending on your isolation requirements.  These include 4 channels of data isolation as well as a 500mW power supply.  They are nearly the same footprint and pin-out as the ADuM140x parts.

    Mark

  • I have to carry an SPI bus at a distance (say, 100 meters), and I am thinking about a schematics with differential (RS422) signals and isolators (something similar to wht you suggest), but I don't know how to bring power to the slave board... is there any solution which also includes power isolation?

    Thanks

    •  Analog Employees 
    over 9 years ago in reply to LEG

    Hello LEG,

    We do not have a complete app note including the required uC portion of the solution.  We have customers that use this solution to speed up their SPI.  I believe they use general purpose I/O and registers to implement the receiver for the delayed data.  You are correct, it would require an independent SPI port with its own clock to simply implement the system.

    MSCantrell

  • I think that is a good solution, but normally the most uC have only one SPI clock line.

    You need an additional external hardware that fulfills your SPI requirements. etc. 24bit ADC with additional 1 byte status word. (32bit SPI)

    Are there application notes available from AD that solves this design solution with uC internal or external Hardware