For optimum performance, an ADCs sample clock inputs (CLK+ and CLK−) should be driven with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional biasing.
High speed, high bandwidth ADCs are sensitive to the quality of the clock input. In order to achieve superior SNR in a high speed ADC, the root mean square (RMS) clock jitter must be carefully considered, based on the requirements for the application’s input frequency. The RMS clock jitter can potentially limit the SNR of even the best performing ADC, exacerbated at higher input frequencies. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by: SNR = 20 × log 10(1/( 2 × π × fA × tJ))
In this equation, the RMS aperture jitter represents the root-mean-square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF under-sampling applications are particularly sensitive to jitter (see Figure 1). As the analog input frequency to the ADC triples using the same RMS clock jitter, the best SNR performance is lowered by 10dB.
The plot below shows the SNR limited performance of various input frequencies across different RMS clock jitter profiles. Notice that as the input frequency increases, a lower RMS clock jitter will be needed to achieve the same SNR limit as seen at lower input frequencies. For example, an RMS clock jitter of 200fs limits an ADC’s SNR performance to no better than 70dB at 250MHz. But, a 1GHz input signal would need an RMS clock jitter of 50fs or better to achieve the same SNR performance of 70dB. Figure 1. Ideal SNR vs. Analog Input Frequency and Clock Jitter
In cases where aperture jitter may affect the dynamic range of the ADC, treat the clock input as an analog signal. To avoid modulating the clock signal with digital noise, separate power supplies for clock drivers from the ADC output driver supplies. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more information about jitter performance as it relates to ADCs.
For clock aperture jitter limit SNR, how to define integrate range (ex:12k-20M) is enough or not?
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