Yesterday, I answered some frequently asked questions on a new 2.0GSPS 12b ADC, AD9625, that was recently released.
As with many GHz ADCs, there are typical questions by system designers about the operation and performance of the ADC. Today, I have compiled some more of the frequently asked questions about this new high speed converter:
The AD9625 provides an internal common mode voltage. The differential input can be AC or DC coupled into the AD9625.
Some GSPS ADCs use an interleaving architecture, with multiple discrete ADC cores, that yield unwanted spurs in the frequency domain. The AD9625 uses a different type of architecture and will not exhibit interleaving spurs.
FFT Plot at 2.0 GSPS, fIN = 1807.3 MHz at AIN (SFDR = 75.5 dBc, SNR = 58.1 dBFS)
The AD9625 has a 1.1V differential input range to achieve full scale.
I have more FAQ for the AD9625 planned for tomorrow.