AD5560: Settling Time and Bandwidth

What are the factors that affect settling time? There are two main factors that affect the settling time. First is the capacitance in the load (DUT). The larger the capacitance in the DUT, the longer the forced voltage takes to settle. The second factor is the compensation. In a very high level, autocompensation usually takes less settling time than safe mode and manual compensation. Other factors include current range settings, the current the load needs, and the magnitude of forced voltage. How long does it take usually before AD5560 force voltage settles? How about MI and MV settling times? For this, we can consult the datasheet. Depending on the load, current range, the magnitude of the forced voltage and compensation settings, the force voltage settling time is varied between tens to hundreds of microseconds. For MI and MV, settling times can reach to up to a few milliseconds due to additional stages the signal will go through which can slow the settling. How is settling time measured? Settling time is measured by forcing a voltage to the DUT and plotting the transition between two voltage levels using an oscilloscope. The figures below show the zoomed-out version of the transition (left) and the point where the terminal voltage settles (right). To objectively decide where the voltage settles, a voltage band is set, which for this example is 10mV. When fluctuations in the voltage are small enough that the measured value never goes out of the band again, it is where the voltage settles. Is measuring settling time at MEASOUT a valid settling time for Force? No. If the parameter to be measured is Force Voltage Settling Time, it needs to be measured at the Force pin. Measuring from the Measout pin will increase the settling time measurements due to additional circuitry that is not part of what’s supposed to be measured. MEASOUT can still be used, if the measurement requires to include the measurement circuitries. Why is it important to spec settling time of a DPS? In many applications, the integrity of measurements as well as how fast the measurements are taken is of the greatest considerations other than the cost. Giving the customers the information on settling time will let them design their application so they can sample right at the moment when the signal to be measured settles, making their system a lot more efficient. Can AD5560 respond to load switching speeds of as fast as 5uS? The response of any DPS to switching loads is limited by settling time. Since AD5560 has settling time of no less than tens of microseconds, it will not be able to handle load switching of speeds as fast as 5uS.

What is the detailed Power Supply Sequencing of AD5560? AD5560 Power Supply Sequencing: AVss -> AVdd -> HCAVss -> HCAVdd -> DVcc It is considered a good engineering practice to always supply power from the most negative up to the most positive supplies. Ho w would the supply affect the Dynamic range? Based on the data sheet, the supplies follow certain conditions and in return, these limits the value of the dynamic range. For example, AVDD must be greater than or equal to 8V while the AVSS must be less than or equal to -5V. Thus, the absolute difference between the AVDD and AVSS (or the workable range) must be greater than or equal to 16V but less than or equal to 33V. Slave FI mode ensures that the current is distributed on all the ganged units. When should I supply HC pins? You should always supply HC supplies. What is the purpose of the diode in series with high current supplies? The diode protects the EXTFORCE1 and EXTFORCE2 output buffers in the event the EXTFORCE1 and EXTFORCE2 output pins were to exceed the HCAVDDx and HCAVSSx voltage levels. In addition, since it is typical that the FORCE pin, EXTFORCE1 pin and the EXTFORCE2 pin are tied together, the diode also protects the EXTFORCEx pin in low current ranges (i.e, using FORCE) wherein the user typically command voltages higher than HC supplies.

For Master FV and Slave FV ganging mode, what should be considered in its implementation? As stated in the Datasheet, “For current to be shared equally, there must be good matching between each of the paths to the DUT”. Current should be shared equally to properly distribute the load and not burden on single unit as this could result to failure. For Master FV and Slave FI ganging mode, why does it have more stability compared to the other mode? Slave FI mode ensures that the current is distributed on all the ganged units.

AD5560: Stability and Compensation

Will ganging mode help the DPS system accommodate >160uF load capacitance? No. The main loop is still controlled by the Master unit and will still obey its own compensation specifications. How can an AD5560 drive a DUT load that has a capacitance greater than the specified max (160uF)? Use Ramp Function to limit voltage rise and prevent undesirable transient conditions.

When the /RESET pin is set to low level, SENSE PIN of AD5560 would consume about 2uA current. Will cause errors in system. How to optimize this error? As the AD5560 is in a pre-POR state because the /RESET is still deasserted, the internals of the chip is not in a nominal state and will tend to show non conformal measurement on any pin. It is recommended that DUT should be fully isolated from the AD5560 until it reaches a known good state or post-POR state. This can be optimized by checking the /Busy state is from low to high that indicates the end of the reset cycle of the AD5560. The duration at which /Busy is set to low can be seen on Figure 4 and specified by t12 at around 400uS. Is this a recommended practice or we should short the DGND pin of the IC to AGND? ADI standard practice is to provide a star ground connection near the point where the power supplies are located. You can also refer to the Tutorial MT031 . Can we use an external trigger for the ramp function? (How do we use ramp function with CL_EN/LOAD/ and HW_INH/LOAD/ pins?) No. Users cannot trigger the start of the Ramp function with any hardware pin. They can only use the software write command(Data = 0xFFFF to Addr = 0x41) to trigger Ramp function. Glitch is observed when transitioning from 0V FV to DPS disable, what are the steps to reduce this? This Glitch is observed due to the loop dynamics involved in the path to the DUT. A big contributing factor to this is the Current Range the AD5560 is in as we change from 0V FV to DPS disable. A workaround proposed to reduce this glitch is to change to the smallest current range possible first, that being 5uA Current range which also uses the largest Rsense before placing the AD5560 to DPS disable. If CS/ is set to high, at what state is SDO? Ideally the SDO pin would be in a High-Z state each time /CS goes high.