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AD5522 Leakage Current Specification

Thread Summary

The user measured significantly higher leakage current (125 uA and 2.8 uA) on the AD5522 evaluation board compared to the datasheet specification (15 nA to 25 nA) when the channel was disabled. The final answer clarifies that the datasheet values are from controlled test environments with minimal parasitics, while the evaluation board introduces additional leakage due to traces and components. The user also inquired about the tristate mode, which is equivalent to setting FORCE1 and FORCE0 to High-Z FOHx, but not suitable for production-level leakage testing.
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Category: Datasheet/Specs
Product Number: AD5522

Hi,

The AD5522 datasheet specifies a "combined leakage at DUT" of 15 nA to 25 nA (Rev. F, page 8). Based on the rows above this one, it appears that this value is "measured with ±11 V stress applied to pin, switch off".

Could you please clarify in more detail the test conditions used for this specification ?

I attempted to measure the leakage current by applying 10 V to the output of a channel while the channel was disabled. In this case, I measured a current of about 125 uA, which is far from the value specified in the datasheet.

My setup was as follows:

  • AD5522 configured using the evaluation board and evaluation software
  • Output voltage is 1 V and channel disabled
  • Measurement repeated using direct SPI commands (same result)
  • Current measured using a Keithley 2450 SMU connected to the "gold pins" labeled RDUT1 on the evaluation board schematic

I also repeated the measurement at 1 V, which resulted in a current of 2.8 uA. These currents change little with each channel or with the reference voltage (5V or 2.5V).

If the "combined leakage at DUT" specification (or the other leakage specifications above in the table) does not correspond to the leakage current when the channel is disabled, could you please clarify what this specification represents and, if available, provide the expected leakage current for a disabled channel ?

Best regards.

Thread Notes

  • Hi,  

    Thanks for your question.

    The figures in the datasheet were from testers which are of controlled enviroment, where measurements were carried out directly from the pins with minimal traces, thus also with minimal parasitics.

    The evaluation board has the part soldered down with quite a number of traces connected to each pin before getting to the test points and gold pins within the board. Leakage current measurements will certainly be impacted by the the parasitics introduced by the traces and other elements in the evb.

    AD5522's evaluation board is designed to help customers evaluate the product's functionality and may not be suitable for a production-level current leakage testing.

    Best regards,
    Mac

  • Hi  ,

    Thank you for the reply.

    I do not believe the evaluation board alone can explain a leakage difference of several orders of magnitude compared to the datasheet specification.

    The datasheet states that the “combined leakage at DUT” is measured with the channel enabled, but tristate. Could you please clarify what this tristate mode exactly is ? The datasheet does not describe it elsewhere, except in the specification table.

    Is this tristate mode equivalent to the High-Z FOHx mode (voltage or current, described in table 26), or something different ? Can this mode be used as a general high-impedance state ?

    Regards.

  • Hi,  

    I am unsure why I am not getting notifications now so I just saw your response.

    Yes. Setting the bits FORCE1 and FORCE0 to High-Z FOHx is equivalent to tri-stating the channel.

    Enabling the channel would require setting the CH EN bit to high.

    Best regards,
    Mac