What causes current clamp drawback?

And why current clamp need a 18% current clamp headroom to maintain FV linearity.

Hi zhuyuqiang,

The requirements you've noted in the MAX32010 datasheet are merely operational requirements of the part to maintain the specified linearity levels. They're repeated in "Note 8" of the Electrical Characteristic section as well.

"Note 8:
In the force-current and force-voltage modes, the reference-clamping voltage CLH must be greater than 0V, and CLL must be less than 0V. For high clamping accuracy, CLH - CLL > 1V. To maintain 0.02% force-voltage linearity when the programmable current clamps are enabled, two conditions must be met: 1) CLH and CLL must be set 12.5% FSR higher than the forced current and 2) CLH and CLL must be set such that CLH ≥ 1.6V + IOSI and CLL ≤ -1.6V + IOSI (e.g., if driving ±1mA in the 2mA range, the current clamps must be set to a minimum of ±1.5mA, or CLH = 3V, CLL = -3V, and IOSI = 0V)."

I'd interpret these restrictions as the range of operation of the internal circuitry such that their individual voltage headroom / footroom minimums are not violated or impinged upon. Very similar to how any discrete BJT clamp would have limitations such that the transistor would maintain a minimum Collector / Emitter voltage, etc.

Regards,

Hooman

Hi Hoonman, thank you for your kindly reply. Could you give the simple current limiting structure of this chip? If the application don't like so big overhead, what can I do? 

Hi zhuyuqiang,

Sorry I don't have access to the design / diagram of the voltage clamp circuitry to share with you. Aplogies.

Regards,

Hooman