KCC's Quizzes AQQ305 about a mutual exponentiation equation
1. Quote of the month: "A train station is where a train stops. A bus station is where a bus stops. I have a work station on my desk, so..." - unknown
2. Quiz AQQ305 about finding a mutual exponential equation
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Quiz: How Well Do You Know Adaptive Power Switching?
Is your I/O module overheating? The AD74416H's Adaptive Power Switching (APS) can cut heat dissipation by up to 40% — but how well do you really understand how it works?
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MAX32010
Last Time Buy
The MAX32010 provides all the key features of a device power supply (DPS) common to automatic test equipment (ATE) and other instrumentation. Its small...
Datasheet
MAX32010 on Analog.com
According to Max32010 datasheet. It has a drawback that The VCLH value is recommended to be a minimum of +1.6V to maintain the FV linearity. I am very eager to find out what is the principle. Could you give a simple schematic about how it works?
And why current clamp need a 18% current clamp headroom to maintain FV linearity.
Hi zhuyuqiang,
The requirements you've noted in the MAX32010 datasheet are merely operational requirements of the part to maintain the specified linearity levels. They're repeated in "Note 8" of the Electrical Characteristic section as well.
"Note 8:
In the force-current and force-voltage modes, the reference-clamping voltage CLH must be greater than 0V, and CLL must be less than 0V. For high clamping accuracy, CLH - CLL > 1V. To maintain 0.02% force-voltage linearity when the programmable current clamps are enabled, two conditions must be met: 1) CLH and CLL must be set 12.5% FSR higher than the forced current and 2) CLH and CLL must be set such that CLH ≥ 1.6V + IOSI and CLL ≤ -1.6V + IOSI (e.g., if driving ±1mA in the 2mA range, the current clamps must be set to a minimum of ±1.5mA, or CLH = 3V, CLL = -3V, and IOSI = 0V)."
I'd interpret these restrictions as the range of operation of the internal circuitry such that their individual voltage headroom / footroom minimums are not violated or impinged upon. Very similar to how any discrete BJT clamp would have limitations such that the transistor would maintain a minimum Collector / Emitter voltage, etc.
Regards,
Hooman
Hi Hoonman, thank you for your kindly reply. Could you give the simple current limiting structure of this chip? If the application don't like so big overhead, what can I do?
Sorry I don't have access to the design / diagram of the voltage clamp circuitry to share with you. Aplogies.
Regards,
Hooman
