Data sheet P42 states that the AD5522 BUSY pin is internally pulled up to 50KΩ.
The evaluation board "EVAL-AD5522" has a 10KΩ pull-up to DVCC, but if there is an FPGA nearby, can it be used without an external pull-up resistor?
Hi mench,
I have an AD5522 that has been working properly for some time (configuring and changing DAC outputs, and adjusting external loops successfully). However, yesterday I discovered a BUSY signal abnormality and can no longer configure the device.
Observed behavior:
1. When the SPI interface is left floating (not connected to any FPGA or MCU) and the AD5522 is not powered, the BUSY pin remains HIGH.
2. After applying power to the AD5522, at the moment when AVDD and AVSS voltage levels change, the BUSY pin changes state (goes LOW).
3. The BUSY pin only returns to HIGH after I power off the AD5522 again.
4. I've also observed the RESET pin (triggered by BUSY's falling edge), and noted that when AVDD and AVSS change state, the RESET pin shows no change.
My questions:
1. Is this behavior indicative of a damaged AD5522, or could there be another issue?
2. If the chip is not damaged, how can I resolve this problem?
PS:
* The yellow line is busy, and the other one is AVDD/AVSS (about 15V)
* The behavior of busy is not exactly the same across the four captures, but there is behavior that is switched on and off multiple times
Thank you for your assistance.
