How to interface AD5522's LVDS to FPGA?

Hello stycle,

I have moved this query to the Automated Test Equipment (ATE) Community. Someone there should be able to assist you better. 

Best regards,
Paul

Hi PaulCA ,

Thanks for moving this inquiry to this forum.

Hi stycle ,

As per the data sheet, AD5522's DVCC can go as low as 2.7V with the LVDS interface.

Table 3 shows that the timing parameters are true if the DVCC used, which is the VCCIO of the FPGA, is at least 2.7V.

It is highly advised to follow the datasheet recommendations. However, should you need to use an FPGA that has interface voltage of 2.5V, note that the timing values from the datasheet may no longer be guaranteed.

One thing you can try is to use the max interface voltage value of FPGA (10CL040) to 2.625V which is much closer to 2.7V and see if it fits better.

Regards,

Menchie

Hi menchie,

    Thanks a lot, Perhaps using SPI may be a better choice.

Regards,

Stycle