The audio codecs in the AD193x family are equipped with a standalone function that allows them to operate directly out of reset without requiring configuration via their I2C/SPI control ports.
Standalone modes are configured by pulling the control port pins either to the supply voltage (1) or to ground (0).
For devices with I2C ports, here are the standalone configuration options:
For devices with SPI ports, here are the standalone configuration options:
The device will constantly check these four pins in order to decide whether to go into standalone mode or not. If the pins are configured in a way that matches one of the configurations shown in the above tables for more than 4 milliseconds, then standalone mode will be activated.
If the pins are then reconfigured (at any time) in a way such that the conditions in the above tables are not met, then the device will revert to its default state (all registers set to their default values) and the device will go into idle mode, waiting to be programmed via the control port.
I have written an Application Note detailing how to use an inexpensive microcontroller to boot up this family of codecs into any desired mode of operation. This is targeted towards an application where there is no system controller or this task would like to be off-loaded to another controller.
Great news! Glad to help. C
Thanks so much for the quick replies. Got our new board working in no time, due to your excellent support.
When the AD193x family parts are put in standalone mode, they perform in the default condition -except for the Internal master clock enable Register 0x00 bit 7; this bit is set to  Enable: ADC and DAC active.
The default condition for the AD193x family has the PLL powered-on and active in 256 x fs, with MCLKI as the PLL input clock, MCLKO in 'XTAL osc enabled,' and PLL clock as the DAC and ADC clock source. The ADCs and DACs are powered up in stereo I2S mode, no mute, no attenuation, 24-bit word width, and the DAC LRCLK and BCLK ports are set to slave mode. The ADC LRCLK and BCLK ports can be set to slave mode by tying the SDA/COUT port Low; the ADC LRCLK and BCLK ports can be set to master mode by tying the SDA/COUT port High.
The sample rate for the AD193x can range from 32 kHz to 48 kHz; the supplied MCLK mus t be 256 × the required fs. For any sample rates outside this window, or if any other modes are required, the AD9193x will require register programming.
Ok, then how about a detailed description of what exactly slave standalone mode and master standalone mode are? Especially with respect to PLL, MCLK, LRCLK master/slave setting, BCLK master/slave setting, etc. Right now the datasheets are extremely vague and I have no idea what the detailed settings are.