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3D ToF Depth Sensing
Clock and Timing
Design Tools and Calculators
Direct Digital Synthesis (DDS)
Embedded Vision Sensing
Energy Monitoring and Metering
FPGA Reference Designs
Interface and Isolation
Low Power RF Transceivers
MEMS Inertial Sensors
Motor Control Hardware Platforms
Power By Linear
Processors and DSP
RF and Microwave
Wireless Sensor Networks Reference Library
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"quad-buffer" headphone amplifier
AD1835: Output filters
AD1835A: DC offset voltage
AD1836: Sampling at 22.05kHz
AD1845: DC offset
AD1852: ESD sensitivity, HBM model data missing from datasheet
AD1853: output impedance
AD1853: Two devices in parallel
AD1854: SPI port unused
AD1871 single ended input range
AD1877: Calculation of the LSB value
AD1937: Failure due to I2C interface
AD1939: datasheet contradictions on SPI timing specification
AD193x family - supporting Sample Rates lower than 32 kHz
AD1955: Independency of the channels
AD1974 Stop Band Filter Response
AD1981 PCB Layout recommendation
AD1986: AC97 code
AD1992: Driving the input stage
AD73311: Power supply
AD73311: Power supply sequencing problem, using DVDD = 3.3V and AVDD = 5.2V
AD73311L: Cascade running at different sampling speeds
AD73322: CD measurability
AD73322: Vref transfer function
AD73322L: Frequency response
AD73360 timing questions
AD73360: Frequency response over sample rate
AD73360: Lower limit of the MCLK
AD73360: Reference voltage
AD73360: SDOFS in figure 10
AD73360: Settling time when changing the PGA gain
AD73360AR: DC performance
AD73360L: Reference does not always power up
ADAU1761: Can I connect one analog and one digital input channel to the ADAU1761 and process both of them together?
ADAU1966 maximum load current
ADAU1966: If using a direct MCLK can I leave LF and PLLVDD pins disconnected?
AVDD and DVDD range
Binary 2.20 format
Can AD1836A work at 32KHz or 44.1KHz sample rate?
Change sample rate by controlling SE pin.
Clicks and pops on power up
Do Analog Devices still have a range of HD Audio Codecs or has this technology all been sold off to Conexant?
Does the AD1852 accept SPDIF format?
Does volume control setting affect THD+N ?
EVAL-SSM2518Z evaluation board documentation and DLL for I2C control
Evaluation board Datasheet
FAQ: Can a digital microphone's PDM output be directly connected to an I2S input?
FAQ: Can MEMS mics be soldered to a flex PCB?
FAQ: Is a microphone with higher sensitivity better than one with lower sensitivity?
Gerber files for Eval board
How do I handle unused digital pins on an AD193x codec?
How to connect unused SDATA inputs on ADAU1966?
How to create an EEPROM image for the ADAU1772 that has different filter coefficients in Bank A and Bank B
I2S interface configuration
Interesting microphone application - "Acoustic telescope"
Long term drift for gain, Uref and FIT data
Low latency audio codec
MEMS microphone IBIS models
New MEMS microphone products
Power supplies, capacitors, and application schematics
Ref out voltage of the EVB
REGEN and THERM pins
Replacement for WM8731SEFL
Request for a 32 bit audio codec
Sample rate lower than 32KHz
SigmaStudio Help File - where could I find it
SSM2250: Replacement type available?
SSM2302: Output overshoot.
SSM2306: Exposed pad connection
SSM2529 Evaluation Board Documentation
SSM2529: Evaluation board documentation
SSM2603 audio codec power supply questions
SSM2603/SSM2604 Boot Sequence
Stand-alone Modes on the AD193x audio CODECs
Temperature drift of the internal PGA
The relationship between value of Input Level Control register (Address 0) and gain value
Unused analog input pin connection
Using ADAU1761 for microphone beamforming
Using ADAU1772 for microphone beamforming
Using LRCLK as PLL input
Video: Getting started with the EVAL-ADMP441Z
Video: Microphone Array Beamforming with the ADMP504
Whether it is pin compatible with TI TPA2010, On-Semi NCP2820?
Why doesn't Analog Devices manufacture 32-bit audio converters?
Working at 8KHz sample rate
Please clarify how the AD1939 decides between Standalone and SPI mode.
As described in the Serial Control Port section on page 14 of the datasheet,
powering up the AD1939 in Stand Alone mode puts the part in default mode with
the exception of the Internal MCLK Enable bit which comes up enabled (Register
0x00 ). This would be defined as 256×fs, I2S stereo, MCLK PLL, 32 kHz – 48
kHz fs window. In Stand Alone Mode, there is no SPI control over the AD1939
until the part is reset by power cycling or toggling the reset pin.
The part is put in Stand Alone mode by holding the CIN (pin 30), CCLK (pin 34),
and CLATCH (pin 35) low at powerup. As shown in Table 11, the state of the COUT
(pin 31) at powerup sets the ADC LRCLK and BCLK ports to be either Master
(output) or Slave (input). This does not have any impact on the SPI comm port
that sets the registers for the AD1939.
Table 11 shows the required state of the 4 SPI port pins to put the AD1939 in
either of the two possible Stand Alone modes.
The AD1939 is always and only a SPI Slave. It cannot act as a SPI Master. The
Master and Slave references are to the ADC clocks, as shown in Table 11.
The Automated Register Window Builder is an application that we have written to
control the AD1939 and other codec products within DAU; it is available on the
AD1939 product page under ‘Tools, Software & Sim Models.’ In conjunction with
our USB interface (EVAL-ADUSB2EBZ), Honeywell should be able to see the
conversation between the software and the AD1939.
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