justified, I2S and TDM mode.
But there is no register descriptions on how to enable right justified and left
The BCLK delay register for ADC and DAC should be set according to the
0 BCLK delay = LJ
1 BCLK delay = I2S
8 BCLK delay = RJ for 24-bit audio in 32 BCLK frame
12 BCLK delay = RJ for 20-bit audio in 32 BCLK frame
16 BCLK delay = RJ for 16-bit audio in 32 BCLK frame
TDM mode supports I2S and LJ modes only.