configuration to him as you suggested before. However, they also would like the
part working at 48KSPS as well. That means, they need 2 crystals in the board.
Now they have designed the board, they asked if they can use the part in slave
mode and provide the required sample clock on ALRCLK and use ALRCLK as the PLL
input. Then they do not need to put another crystal on the board.
The AD1974 PLL will not lock to an Fs below 32 kHz; the part MUST be run in
direct mode. For this application, they are correct that 2 MCLK sources are
necessary. I would recommend that they use 512 x Fs mode when the using Direct
Lock. It would be easiest if they left the PLL off for both modes and switched
only the MCLK frequencies to change modes. I would recommend that they mute the
ADCs during the switch using ADCC0 [5:2].
To save power, they can set
PLLCC0  = 1
For 512 x Fs
PLLCC0 [2:1] = 10
So PLLCC0 = 0x85
They will need a 4.096 MHz and a 24.576 MHz clock. They should set PLLCC1 as
PLLCC1 [1:0] = 11
So that PLLCC1 = 0x03
To mute the ADC:
ADCC0 = 0x3C