ADAU1966: If using a direct MCLK can I leave LF and PLLVDD pins disconnected?

Q 

Regarding the PLL of ADAU1966, I intend to use a 48kHz FS with a
24.576MHz master clock. I can provide all the clocks to the ADAU1966.
Can I completely disable the internal PLL or do I still need to connect the
PLLVDD and LF circuits ?

 

A 

As you are providing a direct MCLK, the Loop Filter components are not required
so you do not need them. The PLLVDD however, involves interfacing inside the
part to other areas. I have asked the designers about this and they have
confirmed that the PLVDD is related to the direct clocking of the part by MCLK
and so you do need to apply power to the PLVDD pin at all times.

Comments
Anonymous
  • over 2 years ago

    Hello Dave

     In the evaluation board(EVAL_ADAU1962A) in place of decoupling capacitors (10uF -5 nos &0.1uF- 6 nos(Analog), 10uF -3 nos &0.1uF- 3 nos(Digital).

    since there are space constraints for my board design.Kindly clarify whether these many capacitors are required else mention the minimum recommended value of decoupling capacitor required for Analog & Digital.

  • over 2 years ago

    Thanks for quick reply,

    Yes i am considering RFI/EMI emission.that's what  i asked you how to terminate that LF pin.Kindly give the any suggestion.

    •  Analog Employees 
    over 2 years ago

    Hello Selvikavi,

    1) You can leave the LF pin floating. I suggest you power down the PLL in the Block Power-Down AND Thermal Sensor Control 1 Register.

    If you have to terminate all pins for RFI/EMI reasons then ask this question again and I will talk to the PLL designer about it.

    2) Thank you for pointing this out. The Theory of operation is correct but the translation from Vrms to Vp-p in the specifications is not correct. It is showing the Vp value. To calculate the peak-to-peak value you multiply the RMS values by 2.828. So it should be the following:

    Differential = 2Vrms = 5.66Vp-p

    Single Ended = 1Vrms = 2.83Vp-p

    I will have to submit a new revision to correct this. It is the same in the ADAU1962A datasheet.

    Thanks,

    Dave T

  • over 2 years ago
    Hi,
     
    1.I am using ADAU1966A Audio DAC in slave mode. MASTER CLOCK is driven from FPGA, So the LF pin is unconnected. kindly suggest how to terminate the LF pin.
    2. In theory of operation of ADAU1966A, it is stated that Each audio pin swings ±1.42V but In specification of Full-Scale Single-Ended Output Voltage says 1.41V (Vp-p). Kindly clarify what will be the voltage swing in single ended and differential.
     
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