Disclaimer: The code and project was tested with the following versions of the sw:
- Xtensa Xplorer 9.0.20
- Xtensa OCD 15.03
- Core Configuration: hifi3z_lark_RI_2022_10
- Xtensa Build Tools: RI 2022_10
- Lark SDK 3.3.1
Master clock on ADAU1860 can be changed on the fly using the PLL to reduce power consumed. This can be done without any audio glitch but in order to do that there are a few steps that needs to be followed.
First it is important to highlight that the clock source must be the XTAL at 24.576MHz.
Look at the code below that changes from the Master Clock of ADAU1860 using the PLL from a given frequency to 98.304MHz.
/*
* First Step is to bypass the pll and use the XTAL.
* That way we can operate and change the PLL avoiding glitches
*/
err = adi_lark_clk_set_mclk_freq(&device, API_LARK_MCLK_FREQ_24P576, true);
/*
* Once the PLL is bypass is time to configure the PLL
* We will configure the XTAL as PLL source and consequently we need to
* configure the PLL with a factor 4x and then update the PLL with the new configuration
*/
err |= adi_lark_clk_config_pll(&device, API_LARK_CLK_PLL_SOURCE_MCLKIN, API_LARK_CLK_PLL_TYPE_INTEGER, API_LARK_CLK_SYNC_SOURCE_INTERNAL, 1, 4, 0, 0);
err |= adi_lark_clk_update_pll(&device);
/*
* Check until the PLL is locked.
*/
adi_lark_clk_get_pll_locked_status(&device, &locked_pll);
while(!(locked_pll & 0x1))
{
err |= adi_lark_clk_get_pll_locked_status(&device, &locked_pll);
}
/*
* Finally configure back the Master Clock with the new clock
*/
err |= adi_lark_clk_set_mclk_freq(&device, API_LARK_MCLK_FREQ_98P304, false);