Q: ADAU1860: Moving audio data to Hifi3z Core Sample by Sample

SampleBySampleDemo.zip Disclaimer : The code and project was tested with the following versions of the sw: Xtensa Xplorer 9.0.20 Xtensa OCD 15.03 Core Configuration: hifi3z_lark_RI_2022_10 Xtensa Build Tools: RI 2022_10 Lark SDK 3.3.1 In the example attached it configures a simple audio Path ADC0 --> Hifi Core --> DAC. It is moving the data sample by sample based on the TIE interface. Look in the Firmware SDK User Guide for more information about the TIE interface in the Data Sync section.

Question 1

ADAU1860: Installing Tools for Xtensa Xplorer

Accepted Answer

Introduction 
 This page is a quick start guide to program and debug on the ADAU1860 evaluation board platform. Here is a summary of what is included in this document: 
 
 Xtensa tool installation on Windows Platform 
 Connecting JTAG probe hardware to the evaluation platform 
 Building programs 
 Linker support Packages 
 Downloading and executing examples provided

Xtensa Tool Installation 
 Hardware requirements. 
 Windows host computer is required to run the following software: 
 
 Xtensa IDE (xplorer) 
 Xtensa XCOD (xtensa on chip debug) daemon 
 
 If you want to use ADAU1860 hardware, then the following components are also required: 
 
 Hardware to drive the JTAG debug interface (e.g. mIDAS-Link) 
 ADAU1860 Evaluation Board Platform 
 Mini USB Cable

Tools install Package and SW Requirements. 
 Core Configuration 
 Those files can be obtained on https://tensilicatools.com/ . 
 RI_2022.10 &rarr; hifi3z_lark_RI_2022_10_win32_redist.tgz 
 SDK 
 Please find latest SDK version from https://www.analog.com/en/products/adau1860.html#product-requirement 
 Xtensa Tools 
 This userguide has been tested using Xtensa Xplorer version 9.0.20, Xtensa on chip debug (XOCD) 15.03 and build tools RI_2022.10. Those files can be obtained on https://tensilicatools.com/ . 
 Installing ADAU1860 Core Configuration 
 
 Click on File | New | Xtensa configuration 
 Select &ldquo;Install a new build from downloaded bundle as the new configuration&rdquo;.

Browse to the downloaded core configuration based on the build tools installed. 
 Select *_win32_redist.tgz for file type.

Press &ldquo;Add Build&rdquo; button and &ldquo;Finish&rdquo;.

Linker Support Packages (LSPs) 
 A linker support package (LSP) specifies object files to pull into an executable using a specific memory map and is used as a convenient short-hand for telling the linker what it needs for a particular target environment. Thus, an LSP ties together components that may need to be adapted as an Xtensa processor is used in different systems, including various portions of the Xtensa software development kit. 
 The gdbio LSP is used to build an application to be executed on a target controlled using an Xtensa debugger and the Xtensa OCD Daemon. It interacts with the debugger to route all file and console I/O, as well as a few other system calls, to the host running the debugger. The C library&rsquo;s standard input and output go to the debugger&rsquo;s console. 
 User can define a custom LSP based on gdbio according to customer&rsquo;s system, here are steps for define customer LSP: 
 
 Copy gdbio LSP provided to desired target path. It can be found on any of the example projects available on the different FAQ pages. 
 Modify memmap.xmm settings if required. 
 Run &ldquo;.bat&rdquo; files attached based on the build tools you plan to use.

Configure Xtensa On Chip Debug 
 This chapter covers the following topics related to configure Xtensa on chip debug. 
 
 Configuring the On-Chip debug. 
 Check XOCD communication. 
 
 It is important to highlight that in order to have Xtensa Xplorer communicating with Hifi3z in ADAU1860. It is important that before powering the board P26 (Self_Boot) and P23 (Rom_Boot) needs to be placed in High position . It is also possible to enable the communication if Power & Clock registers have been configured previously. 
 
 Configuring Xtensa On Chip Debug (XOCD) 
 Here are steps for configuring Xtensa On Chip Debug (XOCD) and making a connection to the XOCD Manager: Before that it is important to highlight that selfboot jumper must be set on high prior to power the board so the HifiCore it is initialize by default. 
 
 Open the Debug Configuration Editor by selecting the menu "Debug->Debug Configurations&hellip;" as shown in next figure.

Create a new Xtensa On Chip Debug configuration as shown in next figure

Check the box "Use OCD Manager". The "Host name" should be "local host", which is the default. The "XOCD Manager Port" should be 20900, which is the default.

Rename the new configuration as you wish.

J-Link (USB) for XOCD / GDB Server Communication 
 Select JTAG Probe by pressing dropdown list and select J-Link (USB), the default JTAG probe speed for communication between the XOCD daemon and the GDB server is 10000000. Please input USB serial number based on your J-Link hardware S/N. 
 
 Diagnose XOCD Server Communication 
 
 Click &ldquo;Diagnose&hellip;&rdquo; 
 Check the box &ldquo;Advance Diagnostic&rdquo; 
 Click "Query" and wait diagnostic finished, XCOD is working if the log as show in next figure.

Import Project / Workspace 
 Import project 
 If the project already exits, we can import it to workspace, here are the steps to import project. 
 
 Open the import menu by selecting the menu &ldquo;File -> Import&hellip;&rdquo; 
 Select &ldquo;General -> Existing Projects into Workspace&rdquo; and click on &ldquo;Next&rdquo;.

Browse and select the folder that contains the project

Click on &ldquo;Finish&rdquo;

Import Workspace 
 If a workspace file was already generated, it can be imported. 
 
 Open the import menu by selecting the menu &ldquo;File -> Import&hellip;&rdquo; 
 Select &ldquo;Xtensa Xplorer -> Import Xtensa Xplorer Workspace&rdquo; and click on &ldquo;Next&rdquo;. 
 Browse and select the folder that contains the workspace.

Select the project and click on &ldquo;Finish&rdquo;.

Running Example on the Evaluation Board 
 This chapter covers the following topics: 
 
 Configuring the target project and core configuration. 
 Compiling and download the program. 
 
 Project configuration 
 
 First select the project.

Then configure the core configuration. In the snapshot attached is using the latest core configuration, but depending on the build tools you might need to use different core configuration.

Go to debug and click on &ldquo;Modifiy" to change the LSP files.

The workspace shared already points to the correct path to the LSP files, but if you have different LSP files to use, browse to the correct folder

Compiling and downloading 
 
 First click on &ldquo;build active&rdquo; to get the code compiled.

Once the code it is compiled, you can click on debug.

Finally click on yes to download the code into the core.

Question 2

ADAU1860: Moving Data to Hifi3z Block Based

Accepted Answer

Disclaimer : The code and project was tested with the following versions of the sw: 
 
 Xtensa Xplorer 9.0.20 
 Xtensa OCD 15.03 
 Core Configuration: hifi3z_lark_RI_2022_10 
 Xtensa Build Tools: RI 2022_10 
 Lark SDK 3.3.1

DMA_FIFO.zip 
 
 In the example attached it configures a simple audio Path DMIC0--> Hifi Core --> DAC. 
 It is moving the data sample by sample based on the DMA and the FIFO. Look in the Firmware SDK User Guide for more information about the DMA and the FIFO interface in the Data Sync section.

Question 3

ADAU1860: Setting an Interrupt on ADAU1860.

Accepted Answer

5417.FDSP_IRQ.zip 
 Disclaimer : The code and project was tested with the following versions of the sw: 
 
 Xtensa Xplorer 9.0.20 
 Xtensa OCD 15.03 
 Core Configuration: hifi3z_lark_RI_2022_10 
 Xtensa Build Tools: RI 2022_10 
 Lark SDK 3.3.1

The following code snippet shows how to configure an interupt using the ADAU1860 SDK. For a full implementation please download the code attached. 
 The code also shows how to use the generated c-files from Lark Studio to load a FDSP program using the Hifi3z Core. 
 
 /* * First is to configure the pin that want to be used as an interrupt source */ 
 err = adi_lark_mp_set_pin_mode(&device, gpio_number, API_LARK_MP_MODE_IRQ_IN ); 
 /* * Now we configure it if we want active high/low/rising/falling edge * and we configure the time debounce to avoid multiple signals */ 
 err = adi_lark_int_set_mp_input_irq_mode(&device, IRQ1, 2); //0 = Active Low; 1 = Active High; 2 = Rising Edge; 3 = Falling Edge LARK_ERROR_RETURN(err); err = adi_lark_mp_set_irq_input_debounce(&device, API_LARK_MP_DEBOUNCE_5MS ); LARK_ERROR_RETURN(err); 
 /* * The interrupts can be linked to 3 different channels MP_IRQ_IN 1, 2 or 3. * In this case we are linking it with the IRQ1. Multiple pins can be linked * to the same IRQ */ 
 err = adi_lark_int_enable_mp_input_irq(&device, IRQ1, (1 << gpio_number), 1); LARK_ERROR_RETURN(err); 
 /* * Then we get the id of the interrupt. */ 
 err = adi_lark_int_get_soc_irq_id(&device, API_LARK_SOC_IRQ_MP_IN_IRQ1 , &button_irq_id); LARK_ERROR_RETURN(err); 
 /* * We clear the interrupt flag before enabling the interrupt */ 
 err = adi_lark_int_clr_mp_input_irq(&device, IRQ1); LARK_ERROR_RETURN(err); 
 /* * Finally we enable the interrupt. * the interrupt is linked with the handler button_irq_handler() that was defined before */ 
 _xtos_set_interrupt_handler_arg(button_irq_id, button_irq_handler, NULL); _xtos_interrupt_enable(button_irq_id);

Question 4

ADAU1860: Changing Master Clock avoiding audio glitches

Accepted Answer

Disclaimer : The code and project was tested with the following versions of the sw: 
 
 Xtensa Xplorer 9.0.20 
 Xtensa OCD 15.03 
 Core Configuration: hifi3z_lark_RI_2022_10 
 Xtensa Build Tools: RI 2022_10 
 Lark SDK 3.3.1

Master clock on ADAU1860 can be changed on the fly using the PLL to reduce power consumed. This can be done without any audio glitch but in order to do that there are a few steps that needs to be followed. 
 First it is important to highlight that the clock source must be the XTAL at 24.576MHz. 
 Look at the code below that changes from the Master Clock of ADAU1860 using the PLL from a given frequency to 98.304MHz.

/* * First Step is to bypass the pll and use the XTAL. * That way we can operate and change the PLL avoiding glitches */ 
 err = adi_lark_clk_set_mclk_freq(&device, API_LARK_MCLK_FREQ_24P576 , true); 
 
 /* * Once the PLL is bypass is time to configure the PLL * We will configure the XTAL as PLL source and consequently we need to * configure the PLL with a factor 4x and then update the PLL with the new configuration */ 
 err |= adi_lark_clk_config_pll(&device, API_LARK_CLK_PLL_SOURCE_MCLKIN , API_LARK_CLK_PLL_TYPE_INTEGER , API_LARK_CLK_SYNC_SOURCE_INTERNAL , 1, 4, 0, 0); err |= adi_lark_clk_update_pll(&device); /* * Check until the PLL is locked. */ adi_lark_clk_get_pll_locked_status(&device, &locked_pll); 
 while(!(locked_pll & 0x1)) { err |= adi_lark_clk_get_pll_locked_status(&device, &locked_pll); } /* * Finally configure back the Master Clock with the new clock */ 
 err |= adi_lark_clk_set_mclk_freq(&device, API_LARK_MCLK_FREQ_98P304 , false);

Question 5

ADAU1860: Moving audio data to Hifi3z Core Sample by Sample

Accepted Answer

SampleBySampleDemo.zip 
 Disclaimer : The code and project was tested with the following versions of the sw: 
 
 Xtensa Xplorer 9.0.20 
 Xtensa OCD 15.03 
 Core Configuration: hifi3z_lark_RI_2022_10 
 Xtensa Build Tools: RI 2022_10 
 Lark SDK 3.3.1 
 
 In the example attached it configures a simple audio Path ADC0 --> Hifi Core --> DAC. 
 It is moving the data sample by sample based on the TIE interface. Look in the Firmware SDK User Guide for more information about the TIE interface in the Data Sync section.

Question 6

ADAU1860: Using SDK to configure Audio Path

Accepted Answer

AudioPathAPI.zip 
 Disclaimer : The code and project was tested with the following versions of the sw: 
 
 Xtensa Xplorer 9.0.20 
 Xtensa OCD 15.03 
 Core Configuration: hifi3z_lark_RI_2022_10 
 Xtensa Build Tools: RI 2022_10 
 Lark SDK 3.3.1

The code below configures an easy ADC --> DAC audio path using the ADAU1860SDK. Look at the attachment for a complete code. 
 
 int32_t err; adi_lark_device_t device = { .cp_mode = API_LARK_CP_NATIVE }; /* disable cache */ xthal_set_region_attribute((void *)0x40000000, 0x20000000, XCHAL_CA_BYPASS, XTHAL_CAFLAG_EXACT); 
 
 /* set REG_DAC_AUTO_MUTE_CTRL_ADDR to disable DAC auto-mute for easy debug */ err = adi_lark_hal_reg_write(&device, 0x4000C054, 0xFF); LARK_ERROR_RETURN(err); 
 /* power up device and audio block */ err = adi_lark_pmu_set_chip_power_mode(&device, API_LARK_PWR_MODE_ACTIVE ); LARK_ERROR_RETURN(err); err = adi_lark_pmu_enable_master_block(&device, 1); LARK_ERROR_RETURN(err); 
 /* set bus clock */ err = adi_lark_clk_set_mclk_freq(&device, API_LARK_MCLK_FREQ_24P576 , true); LARK_ERROR_RETURN(err); 
 /* power on all modules */ err = adi_lark_pmu_enable_master_block(&device, true); LARK_ERROR_RETURN(err); 
 /* ADC0: 96KHz, differential input */ err = adi_lark_adc_set_sample_rate(&device, 0, API_LARK_ADC_SAMPLE_RATE_96KHz ); LARK_ERROR_RETURN(err); err = adi_lark_adc_set_input_mode(&device, 0, false); LARK_ERROR_RETURN(err); 
 /* DAC: 96KHz, from ADC0 */ err = adi_lark_dac_set_sample_rate(&device, API_LARK_DAC_SAMPLE_RATE_96KHz ); LARK_ERROR_RETURN(err); err = adi_lark_dac_select_input_route(&device, API_LARK_DAC_ROUTE_ADC0 ); LARK_ERROR_RETURN(err); 
 /* HPAMP: headphone mode*/ err = adi_lark_hpamp_set_output_mode(&device, API_LARK_HPAMP_HEADPHONE ); LARK_ERROR_RETURN(err); 
 /* Power on ADC0 and DAC */ err = adi_lark_adc_enable_power_on(&device, 0, true); LARK_ERROR_RETURN(err); err = adi_lark_dac_enable_power_on(&device, true); LARK_ERROR_RETURN(err); err = adi_lark_dac_enable_mute(&device, false); LARK_ERROR_RETURN(err); err = adi_lark_dac_set_volume(&device, 0x40); LARK_ERROR_RETURN(err); 
 while(1) { asm( "WAITI 0" ); }

Question 7

ADAU1860: Understanding Priorities in ADAU1860 with XEA2

Accepted Answer

On ADAU1860 there are 2 level of interrupts, high and low. By default all interrupts on ADAU1860 are on low priority and if high priority wants to be set, needs to be done specifically. 
 That is possible on the SDK using the API call adi_lark_int_set_soc_irq_priority ( adi_lark_device_t* device, adi_lark_soc_irq_src_e irq, adi_lark_soc_irq_pri_e pri). 
 If the priority is high, the interrupts are handled following a fifo schedule, the first interrupt that arrives, the first interrupt that is handled. 
 On the other hand, if the priority is low, on XEA2 it exists subpriority by default, so it won&rsquo;t follow a FIFO schedule. The subpriority is defined:

This can be changed recompiling XTOS. Please go to your Xtensa Tools installation path for more details 
 &ldquo;...\xtensa\XtDevTools\install	ools\RI-2021.8-win32\XtensaTools\xtensa-elf\src\xtos\xtos-params.h&rdquo;

Package	Description
ADAU186x SDK	SDK containing API calls to program ADAU1860-1. Available on https://www.analog.com/en/products/adau1860.html
Xtensa Xplorer	GUI to program and debug Hifi3z Code. Available on https://tensilicatools.com/platform/adi-adau1860-1/
Cadence License	License required to compile code for Hifi3z Core Request it on https://tensilicatools.com/platform/adi-adau1860-1/
ADAU1860 Core Configuration	Core configuration required to compile code with ADAU186x as target. It is important that the core configuration matches with the Xtensa Xplorer build tools version. Request it on https://tensilicatools.com/platform/adi-adau1860-1/
Xtensa OCD	Xtensa On chip debug required to debug it. Available on https://tensilicatools.com/platform/adi-adau1860-1/
Memory Template	Available on the different Example Codes More info on “Installing Tools for Xtensa Xplorer” or any of the example code

Package	Description
ADAU186x Hardware Reference Manual	Description of the different peripheral blocks and Registers. Available on https://www.analog.com/en/products/adau1860.html
ADAU1860 EVB SCH	Schematics of the eval board. Available in LarkStudio installation folder or in LarkStudio/Help
ADAU1860 EVB User Guide	Guidance about the different jumpers meaning and configuration available on ADAU186x EVB Available in LarkStudio installation folder or in LarkStudio/Help
Lark Studio Getting Started Guide	Introduction to the different features available on Lark Studio Available in LarkStudio installation folder or in LarkStudio/Help
Xtensa Tools User Guide	Introduction about how to configure different pieces required on Xtensa Xplorer to use it with ADAU186x(Core configuration, Memory map, LSP files). Find it here “Installing Tools for Xtensa Xplorer”
Firmware SDK User Guide	Introduction to the SDK, and explanation about the configuration of the different blocks. Available with ADAU186x SDK Installer

Package	Description
AudioPathAPI	Example that configures basic audio path (ADC à DAC) using SDK API calls. Find it here.
DMA_FIFO	Example that moves data block base to the Hifi3z Core using the DMA and the FIFO. Find it here.
FDSP_IRQ	Example that configures a button from the EVB to trigger an interrupt and changes the bank filter. Find it here.
SampleBySampleDemo	Example that moves data sample by sample to the Hifi3z Core using the TIE interface. Find it here.

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