The MAX98357A follows standard I2S timing by allowing a delay of one BCLK cycle after the LRCLK transition before the beginning of a new data word (Figure 7 and Figure 8 in the datasheet). It is reccomended to follow the polarity of the LRCLK clock and not tie the LRCLK either high or low in the case of custom drivers where I2S is not naturally supported on a microcontroller.