SSM2603/SSM2604 Boot Sequence

When booting the SSM2603 and SSM2604, a control register programming sequence must be followed: CONTROL REGISTER SEQUENCING 1. Enable all of the necessary power management bits of Register R6 with the exception of the out bit (Bit D4). The out bit should be set to 1 until the final step of the control register sequence. 2. After the power management bits are set, program all other necessary registers, with the exception of the active bit [Register R9, Bit D0] and the out bit of the power management register. 3. As described in the Digital Core Clock section of the Theory of Operation, insert enough delay time to charge the VMID decoupling capacitor before setting the active bit [Register R9, Bit D0] . 4. Finally, to enable the DAC output path of the SSM2603, set the out bit of Register R6 to 0. In short, VMID must be at full voltage before you enable the digital core. This FAQ was generated from the following discussion: SSM2604 ADC output

SSM2603 audio codec power supply questions

Q Can I use DBVDD +3.3V when DCVDD, AVDD and HPVDD will be connected to 1.8V ? Is it possible to leave HPVDD unconnected if I'm not going to use headphone outputs? A SSM2603 can work at 3.3V for DBVDD and 1.8V for other supplies. And if Headphone is not used, HPVDD can be left floating.