Request for a 32 bit audio codec

DAC In thread Is volume control in AD1939 analog or digital? Coleman says: The volume control in the AD1939 is digital. Please be aware that attenuating the DAC signal will degrade the DNR of the output. Please consider adjusting the signal level in your system outside the AD1939. I have disussed this issue with others and they all say that adding analog volume control after the DAC is a bad idea. I agree, there will be added analog noise for one thing. The ESS Sabre32 Refrence DAC has a DNR of 129 dB, the AD1939 has a DNR of 112, 17 dB more headroom in the ESS DAC. With 32 bit DAC it will be possible to implement a digital volume control and still have hifi quality. ADC The SABRE32 Reference ADC has a programmable 8-band biquad filter which can be used for (RIAA) equalization. This is very interesting. Conclusion The ESS DAC/ADC combo has a couple of features that I would like to have from Analog Devices in an upgraded AD1939. It has been a long time since you upgraded your audio catalog.

AD1939: datasheet contradictions on SPI timing specification

Q AD1939 datasheet, rev D, Figure 11 shows tCLH from clock rising edge to Latch rising edge. On the otherhand, this timing specification (i.e. tCLH) in the table on page 7 reads: tCLH from CCLK Falling. Can you confirm which is correct? A Figure 11 in the AD1939 datasheet, rev D is correct. This figure shows tCLH from clock rising edge to Latch rising edge. This tCLH timing specification in the table on page 7 needs to be updated to: from CCLK Rising. This will be updated on the next Revision of the datasheet.

Q Please clarify how the AD1939 decides between Standalone and SPI mode. A As described in the Serial Control Port section on page 14 of the datasheet, powering up the AD1939 in Stand Alone mode puts the part in default mode with the exception of the Internal MCLK Enable bit which comes up enabled (Register 0x00 [7]). This would be defined as 256×fs, I2S stereo, MCLK PLL, 32 kHz – 48 kHz fs window. In Stand Alone Mode, there is no SPI control over the AD1939 until the part is reset by power cycling or toggling the reset pin. The part is put in Stand Alone mode by holding the CIN (pin 30), CCLK (pin 34), and CLATCH (pin 35) low at powerup. As shown in Table 11, the state of the COUT (pin 31) at powerup sets the ADC LRCLK and BCLK ports to be either Master (output) or Slave (input). This does not have any impact on the SPI comm port that sets the registers for the AD1939. Table 11 shows the required state of the 4 SPI port pins to put the AD1939 in either of the two possible Stand Alone modes. The AD1939 is always and only a SPI Slave. It cannot act as a SPI Master. The Master and Slave references are to the ADC clocks, as shown in Table 11. The Automated Register Window Builder is an application that we have written to control the AD1939 and other codec products within DAU; it is available on the AD1939 product page under ‘Tools, Software & Sim Models.’ In conjunction with our USB interface (EVAL-ADUSB2EBZ), Honeywell should be able to see the conversation between the software and the AD1939.

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AD1939 Production
The AD1939 is a high performance, single-chip codec that provides four analog-to-digital converters (ADCs) with differential input, and eight digital-to...
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