Working Vs Not working waveform AD1937

Hello Ganesh,

So are these screenshots the I2S output of the AD1937 or input into the AD1937? 

If it is the output, then you are getting data out of the ADCs. I can see the data in your last screenshot.

If it is the I2S input to the codec to send to the DACs, then you are sending data and from what I can see in the screenshot the data looks fine. Is the data changing? In other words, it is not a static DC level? 

So there must be another reason for the lost audio out of the DACs. 

Do you still have MCLK?

There are other pins that might cause an issues. 

Then what are the register settings? 

Have you read back the register settings to verify they are properly getting loaded?

Enough questions for now....

Dave T

Hi Dave, Yes we are using I2S as input only. As using only 1 DAC.

Yes, MCLK is coming fine in both cases 12.288MHz

Have attached our register settings below for both cases.

{ 0, 0x98} ,    /* PLL_CLK_CTRL0: pll input: mclki/xi 12.288Mhz */ //0x81 //0x98
             { 1, 0x00} ,    /* PLL_CLK_CTRL1: no on-chip Vref */
             { 2, 0x00} ,    /* DAC_CTRL0: TDM mode */
             { 3, 0x01} ,    /* DAC_CTRL1: reset */
             { 4, 0x00} ,    /* DAC_CTRL2: 48kHz de-emphasis, unmute dac */
             { 5, 0x00} ,    /* DAC_CHNL_MUTE: unmute DAC channels */
             { 6, 0x00} ,    /* DAC_L1_VOL: no attenuation */
             { 7, 0x00} ,    /* DAC_R1_VOL: no attenuation */
             { 8, 0xFF} ,    /* DAC_L2_VOL: no attenuation */
             { 9, 0xFF} ,    /* DAC_R2_VOL: no attenuation */
             {10, 0xFF} ,    /* DAC_L3_VOL: no attenuation */
             {11, 0xFF} ,    /* DAC_R3_VOL: no attenuation */
             {12, 0xFF} ,    /* DAC_L4_VOL: no attenuation */
             {13, 0xFF} ,    /* DAC_R4_VOL: no attenuation */

Hello Ganesh,

Is the source of the I2S signals coming from a part that is also using the same MCLK that you are sending to the codec? 

PLL+CLK_CTRL0 I am not sure what you are doing there? Are you setting it to 0x98? 

Then I see 0x81 and 0x98? So are you initially setting it to 0x81 then writing 0x98?

With 0x81 you are powering down the PLL. 

In the DAC Control register 1, you are setting it to read the data bits at the end of the cycle. This should not be a big problem so I do not expect this to be the reason.

I see you are muting the unused channels which is fine... 

So I do not see some glaring issue showing a problem of how you are setting up the part.

So I am thinking this is more of a hardware issue with what you have disclosed to me so far. 

You can try to turn on the MCLK output pin and see if you see the correct clock frequency out of that pin. This would validate that the PLL is working and you have an internal clock .

Look at the CM pin. Is that at a correct voltage?

Look at the FILTR pin voltage.

Obviously, checking all the power pins would be a good thing to do. 

I had asked if you read back the registers to verify they were properly written. Have you done that?

By the way, often overlooked when checking power pins is checking the ground pins!!! I have seen bad solder joints on a ground pin cause serious issues. 

Are you using the ADCs? Are those working?

Then one last thing, have you talked to it and asked it nicely to work?  

Enough for now,

Dave T

Hi Dave,

Let me explain the issue in brief. In our design Elkhart lake processor has both in Built CVAS engine and ARM Cortex Core in same chip. Both can drive the Same I2S bus if enabled.

If we are playing Audio from CVAS engine present in CPU, from AD1937 DAC output is generating and audio is playing in speaker.

But we are playing Audio from ARM Cortex core present in CPU, from AD1937 DAC output is not generating and audio is not playing in speaker.

In both the condition PLL is getting locked and we are able to read the IC register which is as expected.

In Both the condition we are maintaining the AD1937 configuration & Hardware Board as same.

How it is playing when is driven from CVAS engine. But it is not playing in ARM Cortex Core.

If you look at the waveform, it looks both are similar when Audio sample comes.

Only difference is BLCK is coming approx. 6ms before the LRCLK. is it expected condition? (CVAS condition)

In Non working condition, BCLK and LRCLK at the same time.(ARM cortex condition)

Always MCLK – 12.288MHz  from Processor. FYI, We are not using ADC.

PLL and Clock Control 0 Register (Address 0, 0x00) :  0x98 (We are writing 98; Only for debugging we just tried 81)

Please help us.

Regards,

Murugesan A

Hi Dave, waiting for your reply

Shall we know wether there is any sequence for clocks to be followed like BCLK should come first then LRCLK any sort of things like that.

Hello Ganesh,

Here are the details of the I2S standard. I think this should be helpful for you.

I2S - Wikipedia

Dave T