ADAU1772 AINx Input Protection and Bias

Hello Neitekiller,

Here is the spec in the datasheet and you did reference this:

Neitekiller said:

The full resolution of the ADC is up to Analog_IN Amplitudes of 2.54Vpp with AVDD=3.3V

1. This can be achieved by either having a strong enough input Signals or..
2. Using the PGA and amplifying the signal to a suitable amplitude

Yes,  A full scale input signal at the pins would be 2.54Vpp. (using 3.3V AVDD). 

Yes, if the signal at the pins was really small, like the output of a mic, then the PGA would be enabled and add more gain. 

Neitekiller said:

• Lets look at an example of a Analog_IN Signal with 5Vpp and 2V offset. After AC-Coupling and biasing of the ADAU1772 the Signal (without clamping) would be 5Vpp with offset of 1.65V (from -0.85V to 4.15V). The clamping clips the Signal at AIN0 to 0V-Vf to 3.3V+Vf.
• Analog_IN Signal with Amplitudes <3.3Vpp won’t be clipped by the external Clampig Diodes.

These two statements I do not fully understand. 

If you put in a 5Vpp signal it would be clipped. Heavily clipped.

I had to look up the diodes you are specifying. They are Schottky diodes and the forward voltage is very low, 430mV. See the datasheet for more details. 

So to forward bias these diodes the voltage on the pin would have to be greater than 3.3V + 0.43V = 3.73V in the positive direction.

In the negative direction it would need to be -0.43V of course. 

These numbers are respective to ground. 

A signal will be riding on the CM voltage of 1.65V on the pin. 

So looking at a signal voltage before the series cap we can see how far positive will it need to go to forward bias the "upper" diode and how far negative to forward bias the "lower" diode. Since the CM voltage is exactly half of the 3.3V this makes the math easy. 

For the positive, 1.65 + 0.43 = +2.08V

For the negative, -1.65 - 0.43 = -2.08V

This is a total peak to peak signal of 4.16V to start clipping the signal from the diodes. 

 Now we do not publish the specifications of the over-voltage protection we have built into the part. It will probably be kicking in with a signal over 0.2V above or below the voltage rails. 

This level of signal would have clipped the ADC long before it reached a p-p voltage of 4.16V. 

The circuit would protect against really large signal swings but there is also over voltage protection built into the pin of the chip. That kicks in but it is when the voltage on the pin exceeds the power rails on the part by around 1V. 

So I guess it would serve to help protect the chip but it would not be clipping the signal before the ADC itself clips, so you are safe there,

Dave T

Hello Neitekiller,

Here is the spec in the datasheet and you did reference this:

Neitekiller said:

The full resolution of the ADC is up to Analog_IN Amplitudes of 2.54Vpp with AVDD=3.3V

1. This can be achieved by either having a strong enough input Signals or..
2. Using the PGA and amplifying the signal to a suitable amplitude

Yes,  A full scale input signal at the pins would be 2.54Vpp. (using 3.3V AVDD). 

Yes, if the signal at the pins was really small, like the output of a mic, then the PGA would be enabled and add more gain. 

Neitekiller said:

• Lets look at an example of a Analog_IN Signal with 5Vpp and 2V offset. After AC-Coupling and biasing of the ADAU1772 the Signal (without clamping) would be 5Vpp with offset of 1.65V (from -0.85V to 4.15V). The clamping clips the Signal at AIN0 to 0V-Vf to 3.3V+Vf.
• Analog_IN Signal with Amplitudes <3.3Vpp won’t be clipped by the external Clampig Diodes.

These two statements I do not fully understand. 

If you put in a 5Vpp signal it would be clipped. Heavily clipped.

I had to look up the diodes you are specifying. They are Schottky diodes and the forward voltage is very low, 430mV. See the datasheet for more details. 

So to forward bias these diodes the voltage on the pin would have to be greater than 3.3V + 0.43V = 3.73V in the positive direction.

In the negative direction it would need to be -0.43V of course. 

These numbers are respective to ground. 

A signal will be riding on the CM voltage of 1.65V on the pin. 

So looking at a signal voltage before the series cap we can see how far positive will it need to go to forward bias the "upper" diode and how far negative to forward bias the "lower" diode. Since the CM voltage is exactly half of the 3.3V this makes the math easy. 

For the positive, 1.65 + 0.43 = +2.08V

For the negative, -1.65 - 0.43 = -2.08V

This is a total peak to peak signal of 4.16V to start clipping the signal from the diodes. 

 Now we do not publish the specifications of the over-voltage protection we have built into the part. It will probably be kicking in with a signal over 0.2V above or below the voltage rails. 

This level of signal would have clipped the ADC long before it reached a p-p voltage of 4.16V. 

The circuit would protect against really large signal swings but there is also over voltage protection built into the pin of the chip. That kicks in but it is when the voltage on the pin exceeds the power rails on the part by around 1V. 

So I guess it would serve to help protect the chip but it would not be clipping the signal before the ADC itself clips, so you are safe there,

Dave T