Hello,
I have a question regarding the AINx Pins of the ADAU1772.
The Datasheet as well as this thread leads me to the decision to implement external protection to the AINx Pins with low Vf Clamping Diodes as shown in the screenshot below.

Then the datasheet and this thread mentions that the AINx Pin will be biased around AVDD/2 after AC Coupling (in my case: 1.65 V).
Am I understanding the following three scenarios correctly?
- Lets look at an example of a Analog_IN Signal with 5Vpp and 2V offset. After AC-Coupling and biasing of the ADAU1772 the Signal (without clamping) would be 5Vpp with offset of 1.65V (from -0.85V to 4.15V). The clamping clips the Signal at AIN0 to 0V-Vf to 3.3V+Vf.
- Analog_IN Signal with Amplitudes <3.3Vpp won’t be clipped by the external Clampig Diodes.
- The full resolution of the ADC is up to Analog_IN Amplitudes of 2.54Vpp with AVDD=3.3V
- This can be achieved by either having a strong enough input Signals or..
- Using the PGA and amplifying the signal to a suitable amplitude
Am I understanding this correctly?
