How to generate HEX file for selfboot

Hello Choe,

The addresses for Flash vs SRAM boot are different, so you need to change your memory map accordingly and regenerate the linker scripts with xt-genldscripts. Here you can see an example of memmap.xmm for use with flash boot:

ROMING=true
VECSELECT=1
VECRESET=0x68000000

BEGIN srom
0x68000000: sysrom : srom : 0x30000 : executable ;
 srom0 : F : 0x68000000 - 0x6802ffff : .ResetVector.text .ResetHandler.literal .ResetHandler.text .srom.rodata .srom.literal .srom.text .rom.store;
END srom

BEGIN dram0
0x5fff0000: dataRam : dram0 : 0x4000 : writable ;
 dram0_0 : C : 0x5fff0000 - 0x5fff3fff : .dram0.rodata .dram0.literal .dram0.data .dram0.bss;
END dram0

BEGIN dram1
0x5fff4000: dataRam : dram1 : 0x4000 : writable ;
 dram1_0 : C : 0x5fff4000 - 0x5fff7fff : .dram1.rodata .iram0.literal .dram1.literal .dram1.data .dram1.bss;
END dram1

BEGIN iram0
0x5fff8000: instRam : iram0 : 0x8000 : executable, writable ;
 iram0_0 : C : 0x5fff8000 - 0x5fffffff : .iram0.text;
END iram0

BEGIN sram
0x60000000: sysram : sram : 0x2F800 : executable, writable ;
 sram0 : F : 0x60000000 - 0x6000017b : .WindowVectors.text .Level2InterruptVector.literal;
 sram1 : F : 0x6000017c - 0x6000019b : .Level2InterruptVector.text .Level3InterruptVector.literal;
 sram2 : F : 0x6000019c - 0x600001bb : .Level3InterruptVector.text .DebugExceptionVector.literal;
 sram3 : F : 0x600001bc - 0x600001db : .DebugExceptionVector.text .KernelExceptionVector.literal;
 sram4 : F : 0x600001dc - 0x600001fb : .KernelExceptionVector.text .UserExceptionVector.literal;
 sram5 : F : 0x600001fc - 0x6000021b : .UserExceptionVector.text .DoubleExceptionVector.literal;
 sram6 : F : 0x6000021c - 0x6002f7ff :  STACK :  HEAP : .DoubleExceptionVector.text .sram.rodata .rodata .sram.literal .literal .sram.text .text .sram.data .data .sram.bss .bss;
END sram

You can use gdbio_sram as a reference for your flash LSP. Then in Xplorer, go to properties, and select your new LSP before building.

You need to rebuild reset_vector.o every time you change the LSP, so I suggest you add the following command as a pre-build step:

xt-clang --xtensa-core=hifi3z_lark_RI_2022_10 -mlsp= .\gdbio_flash -DXTOS_UNPACK -g -c -mlongcalls -mtext-section-literals -I "C:\usr\xtensa\XtDevTools\install\tools\RI-2022.10-win32\XtensaTools\xtensa-elf\src\xtos" -o  C:\usr\xtensa\XtDevTools\install\builds\RI-2022.10-win32\hifi3z_lark_RI_2022_10\xtensa-elf\arch\lib\reset-vector.o  C:\usr\xtensa\XtDevTools\install\tools\RI-2022.10-win32\XtensaTools\xtensa-elf\src\xtos\xea2\reset-vector-xea2.S

When converting the elf file into hex, the addresses should be updated too:

xt-dumpelf --base=0x68000000 --width=32 --full --size=0x30000 --little-endian .\bin\hifi3z_lark_swupgrade\Debug\dmic_dac_flashV2> dmic_dac_flashV2.hex

By following these steps and using selfboot=high, room_boot=high, you should see your program being loaded and executed from flash just after reset. I hope this helps! Please let us know if you encounter additional problems.

Kind regards,
Roberto.

Hello Choe,

The addresses for Flash vs SRAM boot are different, so you need to change your memory map accordingly and regenerate the linker scripts with xt-genldscripts. Here you can see an example of memmap.xmm for use with flash boot:

ROMING=true
VECSELECT=1
VECRESET=0x68000000

BEGIN srom
0x68000000: sysrom : srom : 0x30000 : executable ;
 srom0 : F : 0x68000000 - 0x6802ffff : .ResetVector.text .ResetHandler.literal .ResetHandler.text .srom.rodata .srom.literal .srom.text .rom.store;
END srom

BEGIN dram0
0x5fff0000: dataRam : dram0 : 0x4000 : writable ;
 dram0_0 : C : 0x5fff0000 - 0x5fff3fff : .dram0.rodata .dram0.literal .dram0.data .dram0.bss;
END dram0

BEGIN dram1
0x5fff4000: dataRam : dram1 : 0x4000 : writable ;
 dram1_0 : C : 0x5fff4000 - 0x5fff7fff : .dram1.rodata .iram0.literal .dram1.literal .dram1.data .dram1.bss;
END dram1

BEGIN iram0
0x5fff8000: instRam : iram0 : 0x8000 : executable, writable ;
 iram0_0 : C : 0x5fff8000 - 0x5fffffff : .iram0.text;
END iram0

BEGIN sram
0x60000000: sysram : sram : 0x2F800 : executable, writable ;
 sram0 : F : 0x60000000 - 0x6000017b : .WindowVectors.text .Level2InterruptVector.literal;
 sram1 : F : 0x6000017c - 0x6000019b : .Level2InterruptVector.text .Level3InterruptVector.literal;
 sram2 : F : 0x6000019c - 0x600001bb : .Level3InterruptVector.text .DebugExceptionVector.literal;
 sram3 : F : 0x600001bc - 0x600001db : .DebugExceptionVector.text .KernelExceptionVector.literal;
 sram4 : F : 0x600001dc - 0x600001fb : .KernelExceptionVector.text .UserExceptionVector.literal;
 sram5 : F : 0x600001fc - 0x6000021b : .UserExceptionVector.text .DoubleExceptionVector.literal;
 sram6 : F : 0x6000021c - 0x6002f7ff :  STACK :  HEAP : .DoubleExceptionVector.text .sram.rodata .rodata .sram.literal .literal .sram.text .text .sram.data .data .sram.bss .bss;
END sram

You can use gdbio_sram as a reference for your flash LSP. Then in Xplorer, go to properties, and select your new LSP before building.

You need to rebuild reset_vector.o every time you change the LSP, so I suggest you add the following command as a pre-build step:

xt-clang --xtensa-core=hifi3z_lark_RI_2022_10 -mlsp= .\gdbio_flash -DXTOS_UNPACK -g -c -mlongcalls -mtext-section-literals -I "C:\usr\xtensa\XtDevTools\install\tools\RI-2022.10-win32\XtensaTools\xtensa-elf\src\xtos" -o  C:\usr\xtensa\XtDevTools\install\builds\RI-2022.10-win32\hifi3z_lark_RI_2022_10\xtensa-elf\arch\lib\reset-vector.o  C:\usr\xtensa\XtDevTools\install\tools\RI-2022.10-win32\XtensaTools\xtensa-elf\src\xtos\xea2\reset-vector-xea2.S

When converting the elf file into hex, the addresses should be updated too:

xt-dumpelf --base=0x68000000 --width=32 --full --size=0x30000 --little-endian .\bin\hifi3z_lark_swupgrade\Debug\dmic_dac_flashV2> dmic_dac_flashV2.hex

By following these steps and using selfboot=high, room_boot=high, you should see your program being loaded and executed from flash just after reset. I hope this helps! Please let us know if you encounter additional problems.

Kind regards,
Roberto.