Digital microphone inputs

Hello lukasma,

ADCEN,

Yes, this is not clear on the datasheet. The reason you cannot use both the ADCs and the Digital mics at the same time is because the decimation filters the ADC uses are used to decimate the digital mic signals so you need to turn them on.

lukasma said:

In the same description, it says that when INSEL=1, BCLK = 128 * f_s. But we also set BPF = 0 in register R16, meaning 64 bits per LRCLK frame. Since we also set CONVSR = 0 in register R17, it looks to me that the BCLK frequency should be 64 * f_s?

Yes, again, a bit confusing (I did not mean to be funny by using the word "bit" but I guess it is funny)  The bit clock is what you use to clock the digital mics. It decimates it at a 128x fs rate so the bit clock setting in R16 is overridden when you turn on the digital mics. Plus the ADC filters are set to this decimation rate as well.  You should be seeing a 128xfs rate of 6.144MHz on the bit clock pin. It will also be set to master regardless of the MS bit in R15.

lukasma said:

What does the phrase "The serial port mirrors the converter rates set in this register" mean in the description of CONVSR? Does it mean that the LRCLK will have the frequency determined by the combination of CONVSR and f_s? I.e., with f_s = 48 kHz and CONVSR = 0x00, will LRCLK have a frequency of 48 kHz? And if f_s = 48 kHz and CONVSR = 0x01, will LRCLK have a frequency of 8 kHz?

For this question and your next question I will answer here. 

The sampling rate is determined by the core clock. First you have to understand that this part was derived from the ADAU1761 which has a DSP core. The DSP core's clock rate and thus the rest of the system is determined by the rate that the core runs its program. It runs it once every sample period. The number of instructions is set to 1024 instructions as you noted in the INFREQ register setting. So this means the MCLK frequency in your case, it would be the PLL output frequency if you were using it, it divided by 1024. So 49.152MHz/1024 = 48kHz and this is the base sampling rate. 

Then you can further divide this rate down if you like. So setting 001 of CONVSR is fs/6. In your case with the clocks you have coming in and the INFREQ setting of 1024 you are dividing the 48kHz clock by 6 giving you 8kHz sampling rate. 

You can actually multiply the rate as well with the fs/0.5 setting and get 96kHz! 

I think I covered all your questions. 

Thanks!

Dave T

Well, now we have set the BPF-bits in R16 to both 0x0 (64 bit clock cycles per frame), and 0x01 (32 BCLK per frame), and the bit clock rate on the bit clock pin is 3.072 MHz and 1.536 MHz respectively, not 6.144 MHz which would be expected with 128 * f_s with f_s = 48 kHz. So apparently, INSEL does not override R16. We suspected this, since if we set BPF = 0x03 (128 BCLK cycles per frame), we can not get any audio out from our microphones, since they don't support higher clock rates than 3.3 MHz. So the datasheet should probably be updated, both the formulation about the enabling of ADCs and the bit clock rate in R19, because they don't really line up with reality.