Initiation sequence

Question

Hi! 
 I have some questions regarding the initialization of ADAU1361. I looked at this post: STARTUP, INITIALIZATION, AND POWER ADAU1361 .However, a few things remained unclear to me, and I would like some clarifications. We are running ADAU1361 in main mode, and we don't use the PLL but rather an external clock directly as the main clock. 
 First of all, we would like to power-reset the device. We have a way of pulling AVDD low and then high, is this enough to trigger the POR circuit? It says in the datasheet, page 22, that POR monitors the DVDDOUT, but this is just an internal regulator. Is it connected/related to AVDD? 
 Secondly, in the linked post, the description of a proper start up/initialization mentioned the following steps: 
 
 Apply the power 
 Set the proper divider value/register settings for core clock 
 Apply the MCLK 
 Enable the core 
 
 What exactly does "Apply the MCLK" mean? Does it mean that up until that point in the initialization, the clock should be disabled, or is it fine if it was already running, maybe even before ADAU1361 was powered up? Because right now, the external clock we use sit on an MCU, and that clock is completely independent of the I2S-interface, so it is in no way "synced" with the power up/start up of ADA1361.

DaveThib · Accepted Answer

Hello lukasma, 
 I am sorry this reply is late. This happens from time to time and I do not know why I am not notified of a post. 
 
 You are asking some great questions and some of them are a little difficult to answer. 
 The POR question. This part is an older part so I do not have a designer of this part to ask. I am fairly certain that the DVDD regulator is powered off of the IOVDD supply not the AVDD. The AVDD needs to be clean to keep digital switching noise out of the audio so powering the core DVDD power from AVDD would not be wise. 
 I need to make a comment that is related to some of your other questions. If you shut off the IOVDD but you still have signals like MCLK or GPIO inputs or other clocks on any of the digital pins, then it will violate the MAX voltage on the pin. The max voltage specification is IOVDD + 0.3V so when IOVDD = 0 Then the max voltage on any pin will be 0.3V. If you have a 3.3V clock on the pin then it will forward bias the ESD circuit and try to power up the part from the input pin. This is obviously not good and may also prevent the DVDD regulator from going low enough to trigger the POR circuit. The way around this problem is to use level translators so when you shut off the IOVDD then the codec side of the level translator will also shut off. 
 
 Applying the MCLK... Yes, you could apply it once the power is up. It is best to wait until the registers are set but not a huge deal. If you are not changing any of the PLL registers, then it is no problem at all to have it on and then update any of the other registers. In fact, you need it. You cannot write to any register above R1 if the core clock is not running. The comment was referring to the PLL divider settings in registers R0 and R1. If you are using the default values then no problem at all. You will have to write to register R0 to turn on the COREN bit to enable the internal clocks so you can write to the other registers and of course, to use the part. The is the "Enable the Core" you mentioned in your list. 
 So step 2 in your list is not needed if you are using the default PLL settings. 
 If you are going to shut off the power to reset the part then make sure your system controller stops the MCLK and holds the pin low while the power is gated. 
 I wish I was the applications engineer on this project originally. To not have a reset pin makes no sense. There is even no soft reset either. It is a great part with great features with the exception of the reset issue. 
 Dave T)

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Initiation sequence

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