Lark Studio I2S Playback

Hi Ajit,

Sorry to hear that you are having problems getting the examples to work, I am sure we will find a solution easily.

However, I would like to know what kind of microphone are you using, as some microphones need polarization that the board does not provide. To make things simple, we recommend connecting a phone or computer via 3.5mm jack cable as the signal source. You will need to change the jumpers next to the input jacks to use the single ended input configuration, as the default is differential.

Also, it is important to note that selfboot must be set to low when using Lark Studio; otherwise the DAC will be internally muted.

Please let me know if this fixes your problem.

Kind regards,

Roberto

Hi Roberto,

 Thanks for your response.

 The AIN0 was differential by default, changed the jumpers to use single ended, verified SELFBOOT_EN and it was set to low. Also used audio source from PC connected using 3.5mm Jack to AIN0, headset to output P30. The audio is working now.

While using other example demos like “lark-demo-adc-dac.larkproj” “lark-demo-adc-eq-dac.larkproj” could not hear audio. Tried connecting a MIC to AIN0 and headset to Output no audio was heard. Please let us know if any other changes in setup to be done.

Could you also please let us know if there are any I2S profiles similar to the examples that can be downloaded on the target.

Thanks,

Ajit

Hi Ajit,

About your question why the microphone was not working, Could you describe the connections?
My guess is that maybe the microphones is missing power. ADAU1860 jack connectors does not have mic bias.

There are no examples that follow that exactly audio path but you can do it yourselve. It should be something like this:

That will be configured on the FDSP Tab.

There are a few things that are not define like who will be Driving BCLK and Fsync signals on the I2S communication, Check that the logical levels are fine (ADAU1860 works with 1.8V IO level)

On the power tab you need to power all peripherals that you plan to use. 

It is important that the sampling rates from all the signals match.

Regards, Jose

Hi Jose,

Thanks for your reply, please find more details about our setup and queries

We want to route audio I2S/TDM data from our platform to the ADAU I2S/TDM codec.  ADAU Codec should be in master mode and need to drive the I2S clock. Need to know on how to configure the I2S headers, clocks for generating BCLK and FSYNC clocks and DSP(for mixing the input channels) and route to output speaker on  ADAU, also need to know what registers are set/unset in Lark studio. 

Please help on this.

Regards,

Ajit.

Hi Ajit, 

These are the important registers you need to set:

On the power tab, It is important to enable power to the chip (bring it to active mode) and enable the general_power_block. Also you will need to enable all the peripherals you plan to use. ADCs. DAC, XTAL, Serial Ports (SPT) in and out, FDSP...
On clock tab is important you configure the clocks. in the eval board you there is a XTAL connected to adau1860 at 24.576MHz, I suggest you to go bypass the pll, and configure the clk at 24.576 on the CLK_CTRL13 Register.

You mention that ADAU1860 will generate the clocks for I2S transmition. for that you need to configure SPT#_CTRL2 and SPT#_CTRL3 accordingly. LRCLK (also called FSYNC) will determinate what will be the sampling rate. and have in mind that bclk has to be at least LRCLKC x slot_width x slots (also called channels) you want to transmit.

on SPT#_CTRL1 you will be configuring the shape of LRCLK, if it requires some delay...  In page 13 and 14 of the datasheet you can find more info about it.

Remember that it is important that AMD platform and ADAU1860 supports the same logic level of the signals (1.8V) and that all the sampling rates must match, for that purpose if you need to downsample or increase the sampling rate, ADAU1860-1 has some dedicated blocks for that (Decimators and Interpolators).

Regards, Jose

Hi Jose,

Thank you for the response.

As per your instructions did all the settings, configuring SPT#_CTRL2 and SPT#_CTRL3 for I2S transmission etc. The AMD platform supports the logic level at 1.8V and the sampling rate is also same, with this still there is no audio on ADAU. I tried checking the signals using Logic analyzer but could not see any signals generated. I tried all possible routes when using Serial Audio Port. Could you please let me know what could be missing. Any specific read in user guide/Data sheet could be helpful.

Regards,

Ajit.

Hi Ajit,

I would focus on having clocks out to verify it that works, and then I would look on the data.

With this registers configured like that, you should see clocks on MP3 and MP4

Regards, Jose

Hi Jose,

Thanks for the reply, after checking the clocks and setting as per your suggestion, on the analyzer could see the clock signals.

Now checking for setting the routes and getting the data. The below is what Iam trying. 

The CHIP_PWR is different as you suggested and it is as per the User guide, could still see clock signals. What could be other differences?

Please share I2S schematics which can be used for different use case with fdsp. 

Regards,

Ajit. 

Hi Anuj,

I'm attaching a larkproject with the configuration you were showing and it was tested on my side that works (I can see the signal mixed on the DAC)

Important pieces of the project to look:

on Power Configuration:

CM_STRATUP_OVER --> CM_BST_OFF. we should enable it only during booting, after that needs to be disable to get best performance.

on FDSP Tab:

FDSP_CTRL4 --> Use SAI0 as FDSP_RATE_SRC. If we are not using any other signal, we could use the SAI0 as it is going to be enable. We are setting the SAI0 as 48KHz so if we do not use interpolators, datapath needs to be set at 48KHz

On DAC Configuration:

DAC0_Route: FDSP0 --> I understood that we wanted to output the signal from the FDSP0.

DAC_FS: --> 48KHz. If we are trying to output FDSP0 which clock source if 48KHz

Test_Project.zip

Regards, Jose

Hi Jose,

Thanks for your reply, we now have the audio working with test project you shared. We will try capture path and update you.

Regards,

Ajit

Hi Jose,

We have created a schematic where we enabled SPT0_IN and SPT0_OUT. We selected the source FDSP0 for SPT0_OUT(attached the snapshot SPT0_OUT and schematic of route) We initiated data from the platform to SPT0_IN of codec and playback was successful on speaker. Now initiated record on the platform which takes data from SPT0_out of the codec. the recorded file has noise along with data.

Can you please help us how do we get data without noise from SPT0_IN and SPT0_OUT.

Also please let us know how do we route mic data to SPT0_OUT.

Regards,

Ajit

Hi, 

If the playback data is fine, maybe there is some configuration on the recording device that is not correct.
About how to route data from the mic to the SPT0, The registers SPT0_route selects the output data of the SPT0. Have in mind that the sampling rate selected is 48KHz so either you should capture the data at that sampling rate, or use the decimator/interpolators/ASRCs for that purpose as the data needs to be sent at at the same rate that LRCLK_Rate


Regards, Jose

Hi, 

If the playback data is fine, maybe there is some configuration on the recording device that is not correct.
About how to route data from the mic to the SPT0, The registers SPT0_route selects the output data of the SPT0. Have in mind that the sampling rate selected is 48KHz so either you should capture the data at that sampling rate, or use the decimator/interpolators/ASRCs for that purpose as the data needs to be sent at at the same rate that LRCLK_Rate


Regards, Jose

Thanks Jose for the reply.

Wanted to know how to generate the master clock for 96KHz, 16 channel and 32 bit as could not find in BCLK_SRC.

Also could not find how to configure the clock source for sampling frequency 44.1KHz and 88.2KHz which was required to create routing using these frequencies.

Could you please help us understand how to generate/set the clock for the desired frequencies.

Regards,

Ajit

Hi Ajit,

16 channels at 32 bits with sampling rate of 96KHz is not supported. that means 50MHz bitclock and the maximum bit clock supported is 24.576MHz.
you can configure the sampling rate with LRCLK. and then multiplying per number of channels desired and bits per channel you get the bitclock.

About how to generate 44.1 KHz clock source it is not supported on ADAU1860 driving the clocks.

Regards, Jose

Thanks Jose for the response,

Can you please let us know which ADI codec will support these Sampling freq 44.1Khz, 96KHz etc and corresponding bclk?.

Also wanted to know why in LRCLK all freq ranges like 96k are available  in ADAU1860.

Regards,

Ajit