Use ADAU as Multichannel Measurement Device

Hello Götz

I apologize because the person that is best to respond to your questions is not available until next week. 

I can respond to parts of your questions. 

This part was designed to take in high level voltages with little to few external components required. We did design in an anti-aliasing filter so you should not have to include one on the front end.

This question has me scratching my head a little to understand what you are asking?

Goetz said:

The system must output absolute voltages to user. Which scaling factor do I need to use to scale outputs? Can I assume that 4.5Vrms is full scale?

This is an ADC. So the output is digital not analog. So are you asking about the digital serial data output voltage? This is going to be the IOVDD voltage. 

What a full-scale analog input voltage converts to into a full scale digital 24-bit signal depends on your settings of the front-end Post ADC gain settings. 

You did not mention your system needs? We have the ADAU1978 which is a 2Vrms max input and then the ADAU1977 which is a 10Vrms max input. The rest of the details of these three parts are very similar. 

This ADC is very unusual in that you can take a high level speaker level output and sample it!! 

Regarding your question are the OSR, I can see that the datasheet makes no mention of it. I can see the MCS multiplication rate but that is the PLL settings not the ADC. So I am will forward this over to the engineer who knows the design of this part better than I. 

Edit to my above response:... I got in touch with one of the designers. 

He said the OSR is 128 x fs. The fs is set in the serial port registers because they will run at the same rate as the converters. So internally the serial port and the ADC share that setting. 

Thanks,

Dave T

Hi Dave, 

and thanks for the fast response. As I read my question again it seems a bit confusing. Let me retry. :) 

I'm not using the ADAU in an analog application. I use it for an industrial measurement system. 
As we are measuring sensor signals we have to scale our output properly. 
I was just asking myself what voltage is one quantization level. As I did some research today I figured out, that it seems to be 6.36V/2^23. @0db gain setting. 

Can you confirm this?

Where I'm struggling a bit is the fact, that the datasheet shows full scale differential voltage with 4.5Vrms. But with a range of 4.18Vrms min and 4.82Vrms max. What is a deviation of around 7%. Is this variation component-to-component or operating-time related? Or based on what facts. Can you support with further information? 
Depending on the answer I have to think about a way of calibration. 

Regarding Oversampling ratio and aliasing. As far as I know, also sigma delta can need antialiasing filter. Indeed simple ones because of the high oversampling.

With the OSR I have what I need. 

You mentioned that OSR is set in the SAI_Ctrl=0 register. Is that what you meant with "The fs is set in the serial port registers..."
That raised another question. Bit[2:0] setting several ranges. Unfortunately 51.2Khz is in between. So which to choose? and what is the impact to the OSR? 

Sorry for bothering with additional questions. But the datasheet is not very detailed in internal functions. 

KR

Götz

Hello Gotz,

(sorry that I did not copy and paste to get the umlats! LOL) (I lived in Germany for two years so I know about them)

Let me jump right into the difficult things to talk about. The level variation. The basic answer is that this part was designed for audio not for data so tradeoffs were made and also for data parts the test programs on the production line are often more stringent which makes for more parts failing lowering the yield from the die. This is one of the reasons why the data converters cost more. Since it seems like you are willing to do some calibration you should hopefully be able to satisfy your accuracy needs. This is up to you to determine. 

From my experience testing and qualifying new part designs, it is usually die variations that can cause these sensitivity differences but also temperature. I have had to deal with that on the test bench. Also adding to the complication are the components used in the analog front end feeding the converters but I assume you know a lot about that! 

So you need to be sure the AVDD voltage is stable and does not drift for obvious reasons. Also make sure the AGNDx pins have a good clean path to ground with few noise currents sharing the same path. Yes, eventually all the grounds will be connected together just make sure they are joined as close to where the power comes into the board so shared paths are minimized. It is super easy to just use a big ground plane but I try to avoid that and use an analog ground plane and a digital ground plane where possible. Anyhow, I am wandering a little from your questions... Sorry,... :) 

On to your question about FS. You wish to run at 51.2kHz and we of course do not list that. This comes down to the frequency coming into the PLL and your MCS bit selection. It is detailed in table 9:

This sets the multiplier for the PLL. The idea is to also make the PLL output frequency be the same giving you options for using other master clocks that might be available in your system. 

So if you have the MCS bit set to "001" and you apply a 12.288MHz MCLKIN the PLL will ultimately divide that down by 256 to get the sampling rate. 

So what you would have to do with that MCS setting to get a sampling rate of 51.2kHz is to feed the ADC an MCLK of 51200 x 256 = 13,107,200 Hz.

Then for other register setting you would set it for 48kHz setting to make sure the OSR and other possible things are correct. All the dividers will be expecting the rate coming in to be 256 x fs. 

The similar thing applies for the other MCS settings. 

The SAI_CTRL0 register will set the OSR correctly. So here you just select the 48kHz setting and you will be fine. 

The OSR will be the same ratio. Obviously the actual filter frequency is slightly different since the Nyquist frequency is slightly different but it will all work out. It will still be 128 x fs using the new number for fs.

Thanks,

Dave T

Thank you, Dave, for the detailed response and valuable hints.

One small point is still unclear to me. In the example of the configuration for Fs and OSR, you assume clock generation via MClk. However, we use LR_CLK at 51.2 kHz to generate the sample rate. How should the SAI_Ctrl register then be configured 48kHz or 64kHz? What effect do the two options, 48 kHz and 64 kHz, have on the OSR?

Thanks in advanced and being so patient with me. :) 

Hello Goetz,

Wait,... I think I missed the detail that you are using the LRCLK input from something else to drive the PLL and not using an MCLK in? 

Dave T

Yes, we are using LRCLK for sampling rate generation over PLL. Using TDM mode with 8 channels. MClk is not used. 

Goetz L.

Goetz said:

Yes, we are using LRCLK for sampling rate generation over PLL. Using TDM mode with 8 channels. MClk is not used. 

Wait,... I am not sure what you are saying?  "over PLL"? Do you mean you are NOT using the PLL at all? It is turned off or bypassed? Or do you mean you are driving the PLL with the LRCLK? This last statement is what I am talking about. The PLL must be turned on and used if you are not using any MCLK input. 

It would be really good to see your hardware schematic and the register writes to the ADAU1979. Then a scope screenshot of the TDM signals would be good. Several screenshots to show the channel counts and then zoomed in a little to see the one or two channels of data. I have an older post I did explaining how these screenshots should look like. 
How to Take Meaningful Screenshots of I2S Audio Signals - Q&A - Audio - EngineerZone

Also, with the register writes it would be handy to know what the timing is after powerup and between writes.

Thanks,

Dave T

Sorry for my missleading description. Yes we are using tthe PLL, and configuration is like adviced from datasheet. fro LRCLK. 
So far it works fine. I can see signals, I have the right samplerate. All 8 channels are working. 

The only thing I am asking is: With a sample rate of 51.2kHz on which value I should set in the SAI_CTRL0 register [2..0] for sample rate. As mine is between 32 -48kHz and 64khz - 96kHz. And does this selcted setting has an influence on the OSR and in what manner. 

Thanks in advanced

Götz

Any news on the last question? :) 

KR Götz

Any news on the last question? :) 

KR Götz