adau7118

Hello shandonguniversity,

It would be good to know a little more detail of your hardware setup and what you desire for output?

You mentioned using two ADAU7118 parts. Do you plan on setting up each of them to output eight channels on their own TDM data streams or are you trying to have then use one 16 channel data stream?

I can see from your screenshot that you are operating with a sampling rate of 96kHz. Is that correct?

I do not know what bit-depth you desire? I am making assumptions since you claim the 12.288MHz bit clock is correct. 

So 12.288MHz / 96kHz = 128. 

This means there is space for 128 bits during each frame. 

So 128 bit slots / 8 = 16 bit slots for eight channels. 

So I am guessing you have two TDM data streams not one 16 channel stream because 8 bit data is just not very good. 

My next comment is about the screenshot of the bit clock. It is not a very good looking square wave. It looks like there is a lot of capacitance on the PCB and possibly low drive strength or some sort of sub-optimal signal integrity setup. The valid "high" and "low" times are very short in that signal!

So send over your SigmaStudio file and hardware schematics. For the moment I probably do not need the PCB layout too but a PDF of the top layer might be good. 

Thanks,

Dave T

Hello, Dave

I am using two separate TDM-8. My hardware configuration is as follows: the chip addresses are 0x14 and 0x15 respectively, register 0x05 is set to 0xC1, register 0x07 is set to 0x51, and all other registers remain unchanged. Each chip outputs its own sdata signal.

Regarding the issue you mentioned where bclk is not an ideal square wave, I am not sure if this is caused by insufficient capability of my oscilloscope probes. I previously successfully designed a driver for 8 microphones using the ADAU7118 on my own, and I have not used the SigmaStudio tool yet, QAQ. I will now upload the PDF files of my hardware schematic and top-level design to you.I have another question: are there any points I should pay attention to when designing the PCB? For example, do BCLK and FSYNC need to be length-matched, or should I use as few vias as possible? I am quite worried whether this will affect the ADAU7118 and mic data, because my ultimate goal is to use 64 microphones.

Additionally, I have found that the pdm_clk issue is resolved as long as I do not connect the sdata pin to the FPGA. I do not quite understand the principle behind this.

Thank you.

Hardware schematic:

PDF

PDF

PDF of the top layer:

PDF

Hello shandonguniversity,

You are asking a lot of good questions and this opens up some deep and complicated topics. I will do my best to comment.

I suggest you download the ADAU1452-Rev-D datasheet and look at the PCB Design considerations section. It is near the end of the datasheet. One of the things I talk about in that section of the datasheet is how to connect the EP. It is tough for me to see exactly what you have done but it looks like you connected it with a trace. I see a shadow on the PDF 

Is this just a two layer board? 

I strongly suggest you use at least four layers. It is not as expensive as it used to be many years ago... (I have been doing this for a long time!-LOL) 

The bypass cap for the power is not placed and connected in such a way as to make it the most effective. C9 is the bypass cap.

Again, in the ADAU1452 Rev D datasheet I show how these 0.1uf bypass caps need to be connected to make them the most effective. 

I have seen this make a big difference. 

I have seen problems customers have had that were caused by incorrect bypass caps and incorrect connections to the EP. 

What is key here is to realize that a via is an inductor. Would you place an inductor between the power and the pin? Probably not. 

Here is a link to the datasheet I mentioned above:

ADAU1452/ADAU1451/ADAU1450 (Rev.D)

Regarding the BCLK and LRCLK traces. Yes, it is good to have them be close to the same length but this does not have to be exact and is not a big cause of issues. Stray capacitance can be an issue and also return currents is also an issue. This is where having a single ground plane with few if any traces so it is a solid plane is important. The same goes for the power planes but often you end up having to split it because you have more than one voltage. Just think of the return currents. 

Yes, use as few vias as possible when dealing with clocks and data. The inductance causes reflections and waveform problems. It is impossible to not have any!! So try to use a few as possible. 

shandonguniversity said:

Additionally, I have found that the pdm_clk issue is resolved as long as I do not connect the sdata pin to the FPGA

That is interesting!! What is the state of that pin on the FPGA? What is it set to? An input? Floating? This can add some stray capacitance and that would be my first guess but if it is set to be an input there might be internal pull-ups. Of course, if it is set to be an output would be bad!! 

Since this account is from a school, I suggest looking into signal integrity concepts. This goes into the art form of PCB design. It certainly is an art form for sure and is very creative and I like that. It is a challenge at times!!

Thanks!

Dave T