Wrong PDM clock generated in TDM-8 mode

Hello kkkkk4real,

Is that user name for real?

LOL

This part is rather simple in that it generates the PDM clock based on the settings and the clocks being fed to it. (I know, that is logical and obvious). So something is not set correctly we just have to find it. We tested all of these settings before the part was released and it was all tested before that in simulations. 

The serial port settings will be critical here. What are your settings in Serial Port Controls 1 Register? 

You must set it to 16 BCLKs per slot.

The BCLK delay of one bit or no bits is a little up to you.

You must set it into TDM mode. 

You must enable all the PDM channels. 

Of course the Decimation ratio needs to be set as you also noted. 

What you are generating with the FPGA is correct for a packed 16 bit TDM-8 format. Now you just have to tell the ADAU7118 exactly what your format is so it can set its internal dividers properly. 

What is the FSYNC format? 50/50 duty cycle? I feel that would be best due to the high frequency. If not then how wide is the pulse if you are using a pulse format? This is usually stated in BCLK cycles. One BCLK cycle, two etc...

Usually it is one which for a 19.2MHz BCLK is really short and so it might be getting missed. 

Dave T

Thank you for your previous answer. I have verified the configuration of the registers. First, I performed a full reset on the chip, which should have restored all registers to their default states. Then, I wrote 0xC1 to the REG_DEC_RATIO_CLK_MAP register to set the decimation ratio to 32×. Additionally, I wrote 0x53 to the REG_SPT_CTRL1 register, configuring the serial port for a slot width of 16 BCLKs per slot, 0 delay, and TDM mode. All other registers were left at their default settings.

Regarding the FSYNC clock, I initially generated it with a pulse width of 1 BCLK cycle. I also tried a 50% duty cycle FSYNC, but the PDM clock frequency remained unchanged.

Hello kkkkk4real,

Can you send over the full set of register writes you are using to program the 7118 after reset?

You already told me you are sending it a 150kHz fs clock, (you tired one BCLK pulse and 50/50 duty cycle) and then a BCLK of 19.2MHz. 

I can setup my Audio Precision to produce these same clocks and see what I get here on the bench. 

Thanks,

Dave T

That‘s the data i read from registers after i wrote it.

That‘s the data i read from registers after i wrote it.