ADAU1977 problem

I am assuming the AD1938 is being used to drive the input of the ADAU1977? They have different ranges for input and output voltages this can lead to performance differences.

AD1938 and ADAU1977 are connected to different DSP digital inputs independently, analog outputs of AD1938 are not used at all. So it’s not a “sequential” AD-DA connection.
All the levels above are stated in dbFS (FullScale), so the analog level difference was already taken into account.
The question was actually very practical.
Could it be possible that THD of an operable ADAU1977 is -65db instead of the declared -95db
because of incorrect\bad pins connection, bad supply, etc? Or it’s definitely a sign of broken chip?
Is there anybody observed the same and the chip replacement helped?

Thanks

Serge, 

Are you able to share a schematic?  One other question, if you bypass the ADAU1977 do you see good FFT of the SPDIF output (perhaps a sine wave generated within the SigmaDSP schematic of ADAU1467)?

TestA.dspproj

The schematic attached. The comments inside

galvinpjg said:

if you bypass the ADAU1977 do you see good FFT of the SPDIF output (perhaps a sine wave generated within the SigmaDSP schematic of ADAU1467)?

Sure, The problem I believe is pretty hardware and not the DSP related at all

SergeG, can you also share the hardware schematic (showing the connections for the ADAU1977 and other devices) along side your SigmaStudio project?

Hi,
The schematic of the original board attached.
However the board in the original state fed ADAU1977 with 3.3 v p-p signal and had no BIAS implemented at all.
So I had to make some modifications of the board implementation.

for AD1938 signal path
- ADA4841-s soldered instead of mentioned NE5532-s (to have rail-to-rail output)

for ADAU1977 signal path
- all the existing components (caps, OPAs, etc) were removed from the original board
- on separate breadboard. Generally the schematic is the same excepting.
-- OPA1612 usage
-- +/- 12v power supply (to be able to reach 10v rms diff for 0dbFS)
-- 2 x zener based voltage limiter ( not to exceed absolute maximum rating)
-- external 7.2v BIAS from +12v rail (resistor divider)
-- no SMD caps usage

If the comments are not clear I could draw the schematic by hand

Thanks,.
SergePDF

If you probe different points is the generator producing low distortion?

The generator is fine, just replacing the chip helped

I apologize for my late reply but did replacing the chip resolve the issue?

The chip replacement resolved the problem completely