AD1937 ADC/DAC Gain stability over time. Can the gain be calibrated one time?

Question

Hello everyone, 
 We want to use the AD1937 as an ADC/DAC solution for a vibration control system. For this we want to have excelent ADC/DAC linearity and phase stability of the sampling and the possibility to control the sampling times excaltly. All this is fulfilled by the AD1937. The only thing we are not sure about is the ADC/DAC gain. The data sheet specifies +-10% ADC/DAC gain error (red), which is far outside our requirements of 0.05% (500 pmm). But we are okay with calibrating the gain against an AC voltage reference (e.g. Fluke 5700A) or a reference voltmeter (e.g. HP3458A). An initial calibration after PCB assembly is done anyway to calibrate the frontend gain and phase delay. The gain error drift (green) is specified at 30 pmm/&deg;C, which would be fine since we are mostly in an air conditioning lab. 
 So the question is How stable is the ADC/DAC gain error over time, assuming stable AVDD and stable room temperature? And for scientify interest, where does this large gain deviation come from, some kind of factory trimming for linearity? 
 Thanks for your help in advance

DaveThib · Accepted Answer

Hello BeSeeTek, 
 You offered up some great questions and you did a great job of explaining why you are asking and what is important to you. 
 I do not always see that. 
 The gain error range is high due to that fact that we do NOT trim and gains or other things in production. This keeps the costs down. The SigmaDelta process is pretty good for taking some things out of the equation but there still are some gain stages and current sources that will drift with differences in the silicon from wafer to wafer and from what the designers have explained to me it has a lot to do with the difficulty of maintaining exact specifications of the poly layers which make up the resistors in the design. 
 If you think about it, if the silicon drifts from batch to batch it will be very close on parts that come from the same wafer and certainly parts that are on the same die itself (the same part) they would not be very different from each other. That is evident in the interchannel gain mismatch specification that you will notice is quite tight. So in the datasheet we have to account for a wide variety of silicon skews during production. 
 Let me add one more detail you did not mention. The common mode voltage has a great effect on the performance of the converters. Any drift will show in the specifications and in the gain. I have seen a few customers with exacting requirements shut off the internal CM generator and drive the pin with an external high precision low drift voltage reference. You may want to experiment with this method to see if it makes a difference for your application. 
 The requirement for good phase relationship is taken care of because it is all clocked from the same source and since it is a SigmaDelta the sampling is done simultaneously so there is virtually no phase shift. I suppose if you look close enough there will be some small differences due to things like sampling caps and coupling caps but I am going to guess this is not a concern for you. 
 The only concern I see is for very low frequencies. If you are going well below the 20Hz or 10Hz down to DC and need the DC gain to be really stable and accurate gain, well, this is where a SigmaDelta converter will have a little trouble. For audio it is not a huge deal but for precise data applications it can be a problem. 
 You also mentioned AVDD. This is also very important for it to be very stable to keep the gain from drifting. So use good regulators for your AVDD as well. 
 Let me know if you have further questions. 
 Dave T)

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AD1937 ADC/DAC Gain stability over time. Can the gain be calibrated one time?