External BCLK, Frame Sync and Data to DAC

Sorry I got it, need to config PLL_CLK_CTRL1 to used PLL to avoid jitter

Hello Ziit,

I cannot help you too much with the SHARC part of your project but I can help with the ADAU1962A DAC. 

The pin numbers you mentioned must be for the SHARC because it does not make sense to have BCLK on pin 16.

That is a power pin.

I do want to ask you what are you sending into the master clock MCLKI pin of the DAC? 

This needs to be locked to the LRCLK and BCLK signals. They need to be derived from the same master clock. 

That would cause clicks and pops for sure. Or just the audio muting from time to time. 

Dave T

Hi Dave,

Thank you for your reply. 

Yes, the pin16 that I mentioned in my SRU routine is a pin for SHARC.

Actually, I have my own bit clock, frame sync and data, I sent them physically to some available pin in DAI1 zone via BRKOUT.

bit clock  to pin 16

frame sync to pin 17

data to pin 18

So now I have bit clock, frame sync and data on Pin 16, Pin 17 and Pin 18,

Then, I was using SRU2 function to give bit clock, frame sync and data to DAC trough corresponding pins for DAC. (Pin 05 for bit clock, Pin 04 for frame sync and Pin 01 for data ). It means that different from the original SRU routine in the example code, DAC is on Target mode to receive bit clock sent by me and data for DAC input is now no more from SPORT4A but directly from me (by using SRU2(DAI1_PB18_O, DAI1_PB01_I); /*send data to DAC without SPORTA*/) .

To make this, I change some value in ADAU1962 configuration to let AC be in Target mode. 

Normally I will hear my signal output from J17 Jack on SOMCRR. I actually did but there is jitters in output signal. 

I check many documents on ADAU1962, SC459 and SOMCRR, find out that on Bit 0 of ADAU1962_PLL_CTL_CTRL1, we could coose 0 or 1 to let DAC clock select MCLK from PLL or from MCLKI. Known that one of the advantage of  MCLK from PLL is to avoiding jitters, so I set this value to 0 (it was 1 in original example code). And indeed, with this value being 0, I have no more jitters in my output signal (with the same SRU routine).

If you have any comments, don't hesitate 

Thank you very much Dave

Hi Dave,

Thank you for your reply. 

Yes, the pin16 that I mentioned in my SRU routine is a pin for SHARC.

Actually, I have my own bit clock, frame sync and data, I sent them physically to some available pin in DAI1 zone via BRKOUT.

bit clock  to pin 16

frame sync to pin 17

data to pin 18

So now I have bit clock, frame sync and data on Pin 16, Pin 17 and Pin 18,

Then, I was using SRU2 function to give bit clock, frame sync and data to DAC trough corresponding pins for DAC. (Pin 05 for bit clock, Pin 04 for frame sync and Pin 01 for data ). It means that different from the original SRU routine in the example code, DAC is on Target mode to receive bit clock sent by me and data for DAC input is now no more from SPORT4A but directly from me (by using SRU2(DAI1_PB18_O, DAI1_PB01_I); /*send data to DAC without SPORTA*/) .

To make this, I change some value in ADAU1962 configuration to let AC be in Target mode. 

Normally I will hear my signal output from J17 Jack on SOMCRR. I actually did but there is jitters in output signal. 

I check many documents on ADAU1962, SC459 and SOMCRR, find out that on Bit 0 of ADAU1962_PLL_CTL_CTRL1, we could coose 0 or 1 to let DAC clock select MCLK from PLL or from MCLKI. Known that one of the advantage of  MCLK from PLL is to avoiding jitters, so I set this value to 0 (it was 1 in original example code). And indeed, with this value being 0, I have no more jitters in my output signal (with the same SRU routine).

If you have any comments, don't hesitate 

Thank you very much Dave