Sampled signal to have a too high frequency

UPDATE:

I measured the BCLK and LRCLK and those are approximately 10x as slow as calculated.

The ADC measures with 48 kHz, 2 channels, 24 bits in a slot width of 32 BCLKs. Thus the BLCK should be 3.072 MHz (48 kHz * 2 * 32) but I measured only 327.8 kHz. The same is true for LRCLK which should be 48 kHz but is only 5.128 kHz.

Since I use an oscillator of 12.288 MHz (ECS-2520MVLC-122-8-CN-TR), does it seem to me that the problem has something to do with the ADCs PLL. NOTE: The oscillator is directly connected to the MCLKIN with a 0 ohm resistor.

As mentioned before do I use the frequency multiplication ratio of 256 * fs with the corresponding MCS(bits 2:0) of 001

It seems to me that the PLL is dividing the MCLK by 37.5 (which gives 327.68 kHz) instead of by 4 (which gives 3.072 MHz) for BCLK. And for LRCLK is it dividing by (37.5 * 2 * 32) to get to 5.12 kHz instead of (4 * 2 * 32) to get to 48 kHz. This also corresponds to my approximately 9 times to high measured frequency (37.5/4 = 9.375).

Thus it seems to be a PLL setting that is off. Does anyone have an idea?

TomSalm said:

The ADC measures with 48 kHz, 2 channels, 24 bits in a slot width of 32 BCLKs. Thus the BLCK should be 3.072 MHz (48 kHz * 2 * 32) but I measured only 327.8 kHz. The same is true for LRCLK which should be 48 kHz but is only 5.128 kHz.

Can you clarify this? You are saying the ADC is sending out 48kHz then you are also saying it is sending out 5.128kHz?

What are you measuring at the MCLK_IN pin for the frequency?

Does the waveform look good? You can attach a screenshot. 

You have mentioned some of your register settings. Can you list out all of the registers you are changing from the default settings?

Since it looks like you are using the ADC as the clock master then the master clock frequency is either wrong or the MCS bits and other PLL settings might be wrong. 

I assume this is your custom hardware? What is connected to the PLL_FILT pin? 

Have you checked the PLL Lock bit to see if it is reporting that it is locked?

Dave T

TomSalm said:

The ADC measures with 48 kHz, 2 channels, 24 bits in a slot width of 32 BCLKs. Thus the BLCK should be 3.072 MHz (48 kHz * 2 * 32) but I measured only 327.8 kHz. The same is true for LRCLK which should be 48 kHz but is only 5.128 kHz.

Can you clarify this? You are saying the ADC is sending out 48kHz then you are also saying it is sending out 5.128kHz?

What are you measuring at the MCLK_IN pin for the frequency?

Does the waveform look good? You can attach a screenshot. 

You have mentioned some of your register settings. Can you list out all of the registers you are changing from the default settings?

Since it looks like you are using the ADC as the clock master then the master clock frequency is either wrong or the MCS bits and other PLL settings might be wrong. 

I assume this is your custom hardware? What is connected to the PLL_FILT pin? 

Have you checked the PLL Lock bit to see if it is reporting that it is locked?

Dave T

Hey Dave,

In the mean time did I found the issue.

The grounding of my oscillator was poor, so when the ADC was switched off, was the oscillator signal okay but when the ADC loaded the oscillator, was there no signal at all.

I checked the PLL Lock bit but the PLL was locked to some internal signal and not to the MCKLIN pin. It turns out that de ADC outputs this approximately 330 kHz when there is no signal on the MCKLIN pin. For some reason is the PLL still able to lock without a signal on MCKLIN.

All connections were resoldered and the system is now working as expected.

Thank you anyway for your response.

Tom

Hello Tom,

Thank you so much for taking the time to report back on the forum. This may be helpful to others in the future. 

Yes, the PLL tries really hard to lock to ANYTHING! LOL. In some ways it is too good at locking. What this most likely was is noise in the system and noise on the power and ground planes. If PCB layout is not done well and the bypass caps are not implemented well then there will be noise and the PLL is often the canary in the coal mine and it shows up on the PLL. You probably should look at your PCB layout. Improving it will help your audio performance and also help EMI issues as well.

 Look at this document I wrote for the AD193X codecs. These principles apply to all parts. Also you can read the PCB layout section of the ADAU1452 datasheet but it pretty much is a repeat of this document. 

(+) PCB Layout Best Practices for AD193x codecs - Q&A - Audio - EngineerZone (analog.com)

If you end up needing to re-spin the PCB I would look carefully at how all bypass caps are routed in your system. Not just the ADC. 

Have a great day and I wish you success on your project!

Dave T