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ssm6515 - Low Power Schematic and Layout Review

Category: Hardware
Product Number: SSM6515

Hello team,

Wondering if I could get some input on my schematic for a device for a client. Will the decoupling caps and output stage filters be sufficient? Additionally, are there any pitfalls you all have found regarding layout for the chipset?

All comments are welcome.



  • Hi  ,

    I will look into this schematic for the output stage filters and decoupling caps, and gather as much information as possible regarding any pitfalls to the design. I will hopefully have an answer by early next week. Thanks!



  • Hi  ,

    I was able to complete some performance tests with your suggested Output Stage filtering, and received some feedback in regards to your power supply decoupling design. I will list my comments below: 

    - The 100nF for IOVDD and 10uF + 100nF caps for PVDD should be fine. 

    Please refer to the SSM6515 Datasheet, specifically the Power Supply Decoupling and Layout sections, which disclose the need to place the decoupling caps as close to the pins as possible. Further traces for these decoupling caps could introduce unwanted inductance, which will reduce the effectiveness of your decoupling.

    Please see the attached Excel spreadsheet, which contains performance comparisons for the SSM6515 for both a No-Filter vs Filter performance spec comparison. 


    To summarize, your suggested Output Stage Filtering drew near Datasheet specs for measurements for SNR, DNR, and Output Noise. The only measurement that was showing some differences was a higher THD+N @ 50mW, which was only 4dB higher. 

    So, overall, your output stage filtering looks sufficient.

    Just curious, is this output stage filtering designed for EMI/RF concerns? Otherwise, if not, you could definitely get away with removing them from your design. 

    Please let us know if you have any further questions or concerns, thanks!