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How does ADAU7118 use TDM-4 in Software mode

Category: Hardware
Product Number: audio

How does ADAU7118 use TDM-4 in Software mode

I originally intended to use a sampling frequency of 150kHZ, 32 times the extraction ratio, to get the maximum clock rate allowed by the microphone of 4.8MHZ. A total of 8 channel 32-bit slot MEMS digital microphones were used to obtain a bit clock rate of 38.4MHZ, exceeding the maximum allowable value of 24.576MHZ. So I want to connect each ADAU7118 with 4 digital MEMS microphones to make the bit clock frequency value 19.2MHZ, which is within the allowable range.
I would like to ask how to connect 4 microphones in software mode. Use the software TDM-4 mode, one connection per DAT data pin, or just PDM_DAT0 and PDM_DAT1, two connections to each data line, divided into left channel and right channel? If so, do I need to use the I2C protocol to operate the CHANNEL PAIR AND CLOCK ENABLES REGISTER to disable the PDM clock 1and close the four channels of channel 4/5/6/7? Is there anything else I should be aware of, thank you for your answer

  • Hello WangGuoLong,

    Your analysis was well done. It is a bit of a complicated datasheet. I tried my best to write it as clear as possible. I am to blame for it so I can criticize it. LOL.  The part is fairly simple to operate and yet it is really flexible. So that was difficult to explain. 

    Yes, you feed it a 150kHz fs signal and a bit clock of 128x fs then the part will count the edges and figure out it is a TDM-4 signal with 32 bits per slot. Then it will divide the bitclock to obtain a PDM clock output of 64x fs. In this case that would be 9.6MHz which is too high for your microphones. If you use the part in the hardware mode it will default to 64x fs for the PDM clock so you are correct, you must use the I2C control mode. 

    So you must change the decimation rate register to be 32x. In the SigmaStudio GUI it is here:

    Note that normally I would recommend you turn on the HPF but in this case I wanted to see the channels on the screenshot below. Otherwise, the rest of the settings should work fine for you. 

    On this next page I set the TDM Tristate registers to tristate for channels above the fourth channel. However, you do not have to set it this way because the part will never get to the upper channels anyway because the next frame will start and that starts it all over again. 

    The screenshot below is the results I obtained when sending the part a 150kHz fs signal and a 19.2kHz bit clock. You can see the blue line is the PDM clock and it is running at 4.8Mhz since it is set to 32x fs. 

    The red lines you can see the data. Since I did not have a mic connected the pin was sitting at ground which is a max negative number. This allows you to see the MSB=1 and the rest of the bits=0. That is a max negative number. You can see there are four channels being displayed per frame. This was why I did not engage the HPF. I wanted to see the data for each channel.  

    This is the register you need to change:

    I think all the others would work with the default settings. 

    Yes, I just verified that. I powered down the part. Powered it back up and loaded the SigmaStudio project settings by doing a read-All from the part. I saw the PDM clock at 9.6MHz. I changed the PDM Decimation rate to 32x and the clock changed to 4.8MHz and everything else looked fine. 

    As I said earlier, I suggest you enable the high pass filter. It is good to not have full scale DC in case something goes wrong with the mic and the data line is either sitting low or high producing a MAX DC level. Speakers tend not to like that! LOL

    Thanks,

    Dave T

  • Hello, thank you very much for your answer. At the same time, I would like to ask how to connect 4 microphones in TDM-4 software mode. Do you need to separate the left and right channels

  • Hello, for his startup time, what is the need for 64 sync frames? Are FSYNC and BCLK sent together? Can I read the data on SDATA only after 64 FSYNC, that is, after the 65th FSYNC%MCEpastebin%

  • If I use the IIC protocol to modify its register, will I have to wait until 64 frames are synchronized before I can do so? In software mode, does the rising edge of FSYNC need to appear together with the falling edge of BCLK? Can FSYNC appear on the rising edge of BCLK