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ADAU1978 Oversampling

Category: Datasheet/Specs
Product Number: ADAU1978


I've been looking into audio ADC's and based on my research do I think that the ADAU1978 works for my application.

I was wondering if it is possible to do internal oversampling inside the chip. I want to sample at 192kHz but output the data at 48kHz.

I did see that there are multiple settings to set the sampling frequencies, but it is not clear to me if the above mentioned oversampling is possible.

Also do I want to know how the characteristic of the digital filter looks like at 192kHz since the digital filter in the datasheet is based on 48kHz.

Look forward to a response.


Thread Notes

  • Hello Tom,

    This part is a Sigma-Delta type of converter so by design it is an oversampling converter. It samples as a 1-bit converter at 6.144MHz and then decimates this down to a lower sample rate and to 24 bits. the lower sample rate is what you set in the registers. So it will decimate by 128xfs to go from 6.144MHz down to 48kHz. If you set it to 192kHZ it will decimate at a 32xfs rate. 

    No matter what end sample rate you choose, it will initially sample at the 6.144MHz rate. 

    I hope that helps.

    Dave T

  • Hello Dave,

    Thank you for the reply.

    I saw the main clock (MCLKIN) in table 9 and understand that when you sample at 6.144MHz and decimate by 128 that you will get to 48kHz. What I don't understand is that with a main clock of 6.144MHz and a 24 bit resolution, will the sampling be done at 256KSPS. Decimating this by 128 will result in 2KSPS which is not equal to 24 bits at 48kHz. Or do I look at this the wrong way?

    Also did I have a question regarding the stopband of the decimation filter. What is the maximum frequency of the stopband? Is this limited by the sample frequency (as can be seen in figure 12) or is this stopband (theoretically) endless? The reason why I ask this, is because I need to determine my analog anti-aliasing filter.

    Best regards,


  • Hello Tom,

    The main clock coming into the MCLKIN pin will go through a PLL where it will be multiplied up to a higher rate. This is why in Table 9 you have to set the MCS bits correctly for the frequency you are feeding to the part. Notice that the selection for a 6.144MHz MCLKIN frequency you use the MCS bits setting of ob000. This is because the PLL will be setup to produce the same output frequency that it is being fed with. It will clean it up but not divide or multiply it. All those settings will result in an internal clock of 6.144MHz. If you do not set these properly the performance will suffer. 

    Yes, the stop band for the filter goes on past the end of the graph. Generally this becomes so high that stray capacitance on the PCB will filter out those higher frequencies. The stop band attenuation is a min of 79dB which is quite good. This is the minimum and you can see where it is on the graph. Since this is a digital filter it will be exactly the same for every device. I did notice that we did not recommend or show any kind of anti-aliasing filter on the inputs. Only a high pass filter because of the common mode voltage. If you are really concerned about aliasing then you certainly can put in a small RC filter at the front end or a small cap between the two input pins to reduce any energy well above the audio band. 

    This part was designed to be able to work on some basic ANC applications where latency is a huge factor. So the digital filter was optimized for low latency which trades off for stop band attenuation. Yes, it would be great if it were >90dB 

    I know nothing about your application but if aliasing is a large concern then perhaps operating the ADC at a higher sampling rate then decimating it down to 48kHz elsewhere in your system will give you the ability to easily filter out energy that is above the Nyquist. If you are using a SigmaDSP then it is easy to run it through an ASRC to bring the sampling rate down to 48kHz from a higher rate. 

    Dave T