Hi Team
As we have used AD1937 in our design we would like a technical team to review and give a feed back on it.
Kindly help us in this regards.
I have attached schematics file for your reference.
Hello Irshath,
Thank you for allowing us the opportunity to review the design before you build the first unit.
I noticed a discrepancy on the bypass caps. You have four 0.1uf caps on the +3.3A voltage line but there are only two DVDD power pins and you have two 0.1uf caps on the V3P3_AUD voltage rail but there are four AVDD power pins. So I think these are backwards. Move two of the 0.1uf caps over to the AVDD pins. Each pin requires its own bypass cap.
You are missing the loop filter for the PLL. You must have it. This is the LF pin, pin 61. See the datasheet for values and how to connect the filter. It does not go to ground.
You have the P_D/RST pin defaulted to be pulled low. This will hold the part in reset. So pull that line high and you should put a 0.1uf cap on the pin as well since you have a rather high impedance 4K7 resistor to pull it up. So you do not want noise to trigger a reset. So stuff R2531 and DNS R2530
Analog Ground and Digital Ground... This is a tricky subject and I have seen this from several different angles. You can certainly try to do what you suggest with tying the two grounds at one point. However, inside our part the two grounds are tied but not exactly zero ohms. It is best to have one ground plane for the entire circuit around the codec. You can choose to use an analog ground for the OpAmps since they are operating differential on the input side. What will be VERY important is the PCB layout. Properly connecting the bypass caps to the pins and planes and then controlling and ground fill on the top layer to keep it away from the ground pins and to not tie to the bypass caps before the connections to the planes. This document details all this. I strongly recommend you follow my recommendations.
(+) PCB Layout Best Practices for AD193x codecs - Q&A - Audio - EngineerZone (analog.com)
By the way, I was in Bangalore this past summer! Lovely city. It helped me to not complain as much about the traffic in Boston. 
Dave T
Hi Dave
Thanks for your response
Updated the capacitor as per your review comments.
For PLL loop need some more clarity
P_D/RST has been corrected as per your review comment
Ground has been changed to single ground.
Kindly give us your feedback on the updated section.
Please find the attached updated schematics file for your reference
Regards,
Irshath
Hello Irshath,
The loop filter itself looks great but DO NOT connect it to ANYTHING else!
There are different filters if your clock source into the PLL is at a very different frequency. There is a recommended filter if you use a master clock up in the megahertz region and a different filter if you use a sampling rate clock in the kilo-hertz region. However, there is no connection to those clocks. The LF pin only comes out of the part for the purpose of connecting a filter between the LF pin and the AVDD power. No other connections should be done to this node.
Thanks,
Dave T
Hi Dave,
Thanks for your response corrected the schematics as per your review comments.
Kindly share us your thoughts.
Regards,
Irshath
