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ADAU1961 resetting LRCLK when in master mode

Category: Datasheet/Specs
Product Number: ADAU1961

We are using an ADAU1961 configured as what the datasheet describes as "master" mode to send audio data from an analog microphone. 

MCLK is originated by a microcontroller, the codec creates the BCLK and LRCLK based on it's PLL configuration.

It works well, except when we need to restart the audio stream. Many times, the LRCLK gets out of sync.
The IC does not have a reset pin.

My question is: Is there a way to reset the LRCLK outside of power cycling the codec?

thank you!

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  • Hello davedesro,

    You are really pushing on a sore spot for me!! Had I been on the design team for this part things would have been different!! There is no way to reset the counters that count the LRCLK period off of the internal master clock. There is no reset pin as you noted. Even if there was a reset pin it would still not have helped because the timing of the internal PLL locking can be slightly different from startup to startup and certainly part to part. 

    I assume you either need to synchronize multiple ADAU1761 DSPs to have the same LRCLK edge or you need to synchronize it to something else in your system? 

    What may be possible is to operate the device as a clock slave. There is one good improvement we started with this DSP and it is on all of our DSPs since then, is a Start Pulse register. This allows you to start running the program based on an external clock. So you set the serial ports to shift in the data using the external clocks then at the end of the frame when the LRCLK changes the new samples are ready to be picked up and the start pulse is generated so the program starts executing to process this new data. 

    I do not know any of your system details so I am not sure what will and will not be possible. 

    Dave T

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  • Hello davedesro,

    You are really pushing on a sore spot for me!! Had I been on the design team for this part things would have been different!! There is no way to reset the counters that count the LRCLK period off of the internal master clock. There is no reset pin as you noted. Even if there was a reset pin it would still not have helped because the timing of the internal PLL locking can be slightly different from startup to startup and certainly part to part. 

    I assume you either need to synchronize multiple ADAU1761 DSPs to have the same LRCLK edge or you need to synchronize it to something else in your system? 

    What may be possible is to operate the device as a clock slave. There is one good improvement we started with this DSP and it is on all of our DSPs since then, is a Start Pulse register. This allows you to start running the program based on an external clock. So you set the serial ports to shift in the data using the external clocks then at the end of the frame when the LRCLK changes the new samples are ready to be picked up and the start pulse is generated so the program starts executing to process this new data. 

    I do not know any of your system details so I am not sure what will and will not be possible. 

    Dave T

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