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Audio DAC via I2S and delay issue

Category: Software
Product Number: AD193X

Hi everybody

in our project  sample rate will be 48Khz and 24bit per sample. I have a question about this protocols. when we use I2S data will be send in serial mode.So imagine we have two DAC and we start to send data via I2S, at this time our first slot (the first half of LRCLK) will be DAC1 data and next half will be DAC2 data. in this situation what will the output of the first DAC be during the time we are in the second half of the wave and are sending data to the second DAC? Will the output of the first DAC be zero until the protocol reaches the first half of its LRCLK again, which corresponds to sending the data of the first DAC? Or will it keep its previous output? Or maybe the output of DACs is activated only when the data of both DACs has been received. Because I didn't find any information about whether these DACs have a buffer to store data or not or ether a pin for enable DACs out put when our data transfer has been completed. Different methods I have seen before in other category of DACs, for example, these converters have two registers to receive data and ping-pong buffering, one register to load the DAC input and the other one somehow The auxiliary register is used to store the next data. Considering that I2S is a serial protocol, how can the delay problem that I mentioned above be solved?

  • Hello ELEC23,

    This is a good question and one that is fairly simple so it tends to not be mentioned in datasheets. For parts that are designed for audio they are designed to gather data for one frame of data and then transfer it to the DACs at the end of the frame. There may be data converters that operate differently but audio converters all function this way. Plus, they all use 2's compliment data format but that is another subject. 

    So what happens is that the data is shifted into large shift registers. Most parts can handle many different audio formats so how it accesses and fills up these shift registers may differ. It depends on the internal digital design but you need not be concerned with the details. Many parts can do up to 16 channels TDM-16 for each frame, not just stereo so this shift register will be deep enough to gather 16 channels of data.

    In all cases the data is shifted in and when the end of the frame is reached, the data in the shift register is transferred in parallel fashion into memory locations that the DACs use to get their samples from. Then the DAC will change to this new output level and the next frame of data will start shifting in. This is also why you need to setup the serial format because the part needs to know where in the large shift register the 24 bits of data for all the channels will end up. 

    By the way, this is one reason why the I2S format has a one bit clock delay at the start of the frame. It gives the logic time to sense the end of frame and then do the transfer. 

    The result is all of the new channels of data are presented to the DACs at the same time. The only delay you get is the time to shift in the frame of data. So one sample period to transfer the data. 

    Dave T

  • Hello to everyone and especially Dave,

    Thanks again for your great detail I understand it completely.Now I have a another question Dave. What will be the output of DACs during that delay (Shift delay)? the output will be zero?or they hold their last state?

    thanks for your time.

  • Hello ELEC23,

    They will do what is called a Zero Order hold. Which despite the name does not mean that it goes to zero. That would be "Zero Insertion", It simply holds the value until the next time it is updated. Of course there will be a small period of time where it is slewing to the new level due to capacitance and drive impedances but it will be quite quick and usually the change from one sample to the next is not much. So it will hold its last state. 

    The result will be a stairstep waveform if it is not filtered at all. Often there is a filter on the output of the DAC so it can be difficult to see the stairstep waveform. 

    You will see this in a lot of parts when they lose their clocks they will stop on the last value and put out a DC level. Most DACs are smarter and will mute if clocks are lost. 

    Dave T