Multi channel Audio Codec

Hello ELEC23, (or do you go by the name "Codec?)

Yes, you can set these up to sample simultaneously. 

If must set them up as either both as a slave to external clocks or setup one of them to be the master and the other the slave.

You need to send the same master clock source to both units. You will most likely have other parts in your system that will also need the same master clock so use a clock buffer to distribute this clock. 

Even if you have the same master clock, you must run one as a slave. The reason is that the counter that creates the LRCLK internally will start counting only after the power has stabilized AND the PLL has locked to the master clock. This will never happen at exactly the same time in two parts so the LRCLK edge will be slightly off between one and the other. This will vary from power up to power up. The way to avoid this is to use the same LRCLK and BCLK for both the ALRCLK and ABCLK pins on both parts. 

Your second question is a little more difficult to answer quickly. I2S is a standard that is a stereo standard. Two channels on one data line. This is why you see our part has two ASDATA Pins. Two channels for each pin. If your microcontroller has four serial data pins then you can take in the eight channels on four pins. 

If you do not have that many pins then it starts getting more tricky and there are a lot of options. You can run it in TDM mode. TDM can be two channels but it can be many more channels and many slightly different formats like number of bits per channel slot and if the data is left justified or right justified and if it is delayed by one bit or not. Then you can setup the part to put out TDM4. Then you can bring in the either channels on two pins. 

If that is still too many pins then you can take advantage of one of the tricks this part can do. It has the Aux mode. In this mode you can take the data from one of the codecs (the first one) and feed it to the second one and set them up to run at a TDM8 rate. Then the four channels from the second codec comes out first and then the four channels from the first codec. With no delay added. Then you would need only one pin for the 8 channels. 

Now we have not discussed the DACs. The discussion is similar but now we are dealing with 8 DAC channels per codec. 

One other thing you have not mentioned is your sampling rate? 

If you are running higher than 48kHz then you will be limited in how fast you can operate the part and how many channels on one line. At 48kHz you are good up to 16 channels of TDM data provided your PCB layout is good. 

96kHz you are limited to TDM eight

192kHz you are limited to TDM four. 

Dave T

Hello ELEC23, (or do you go by the name "Codec?)

Yes, you can set these up to sample simultaneously. 

If must set them up as either both as a slave to external clocks or setup one of them to be the master and the other the slave.

You need to send the same master clock source to both units. You will most likely have other parts in your system that will also need the same master clock so use a clock buffer to distribute this clock. 

Even if you have the same master clock, you must run one as a slave. The reason is that the counter that creates the LRCLK internally will start counting only after the power has stabilized AND the PLL has locked to the master clock. This will never happen at exactly the same time in two parts so the LRCLK edge will be slightly off between one and the other. This will vary from power up to power up. The way to avoid this is to use the same LRCLK and BCLK for both the ALRCLK and ABCLK pins on both parts. 

Your second question is a little more difficult to answer quickly. I2S is a standard that is a stereo standard. Two channels on one data line. This is why you see our part has two ASDATA Pins. Two channels for each pin. If your microcontroller has four serial data pins then you can take in the eight channels on four pins. 

If you do not have that many pins then it starts getting more tricky and there are a lot of options. You can run it in TDM mode. TDM can be two channels but it can be many more channels and many slightly different formats like number of bits per channel slot and if the data is left justified or right justified and if it is delayed by one bit or not. Then you can setup the part to put out TDM4. Then you can bring in the either channels on two pins. 

If that is still too many pins then you can take advantage of one of the tricks this part can do. It has the Aux mode. In this mode you can take the data from one of the codecs (the first one) and feed it to the second one and set them up to run at a TDM8 rate. Then the four channels from the second codec comes out first and then the four channels from the first codec. With no delay added. Then you would need only one pin for the 8 channels. 

Now we have not discussed the DACs. The discussion is similar but now we are dealing with 8 DAC channels per codec. 

One other thing you have not mentioned is your sampling rate? 

If you are running higher than 48kHz then you will be limited in how fast you can operate the part and how many channels on one line. At 48kHz you are good up to 16 channels of TDM data provided your PCB layout is good. 

96kHz you are limited to TDM eight

192kHz you are limited to TDM four. 

Dave T

Hello again, thanks Dave for your detailed answer.Dave our sample rate will be 48Khz and 24bit per sample. I have another question about this protocols. when we use I2S data will be send in serial mode.So imagine we have two DAC and we start to send data via I2S, at this time our first slot (the first half of LRCLK) will be DAC1 data and next half will be DAC2 data. in this situation what will the output of the first DAC be during the time we are in the second half of the wave and are sending data to the second DAC? Will the output of the first DAC be zero until the protocol reaches the first half of its LRCLK again, which corresponds to sending the data of the first DAC? Or will it keep its previous output? Or maybe the output of DACs is activated only when the data of both DACs has been received. Because I didn't find any information about whether these DACs have a buffer to store data or not or ether a pin for enable DACs out put when our data transfer has been completed. Different methods I have seen before, for example, these converters have two registers to receive data, one register to load the DAC input and the other one somehow The auxiliary register is used to store the next data. Considering that I2S is a serial protocol, how can the delay problem that I mentioned above be solved?