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规格书问题 - Translation: Specification issue

Category: Datasheet/Specs
Product Number: AD2428

1、我正在用AD2428做一种公用的通信模块,开放一些接口输出,目前在了解规格书一些使用操作。其中有一个地方就是ADR1/IO1这个管脚我可以通过编程配置复用成CLKOUT1输出,把他用来做ADC或者DAC或者同步整流器的输入主时钟,这个功能挺好的。我查看了对应的A2B_CLK1CFG配置寄存器,然后对有个地方不是了解,就是这个CLKOUT1竟然还可以配置成取反,没有理解在应用场景上上有什么用?TRANSLATION: I am using AD2428 to make a public communication module and open some interface outputs. I am currently learning about the specifications and some operations. One of them is that I can multiplex the ADR1/IO1 pin into CLKOUT1 output through programming configuration, and use it as the input master clock of ADC or DAC or synchronous rectifier. This function is quite good. I checked the corresponding A2B_CLK1CFG configuration register, and then I didn’t understand one thing. That is, CLKOUT1 can be configured to be inverted. I didn’t understand its use in application scenarios.

2、我看里面有提到一颗A2B芯片,可以最多挂4个数字PDM麦克风,这四路PDM数据是同时直接走A2B总线,是这个意思吗?能给我简单说下,我在DEMO板上看下吗?TRANSLATION: I saw it mentioned that an A2B chip can be connected

to up to 4 digital PDM microphones. These four channels of PDM data are sent directly to the A2B bus at the same time. Does this mean? Can you briefly explain it to me? Can I check it out on the DEMO board?

3、没有理解I2S RX数据在1个超级帧里面有上游和下游都传输的情况?是不是我本身理解错了?TRANSLATION: Don’t you understand that I2S RX data is transmitted both upstream and downstream in a super frame? Did I understand it wrong?

[edited by: GenevaCooper at 1:55 PM (GMT -4) on 19 Sep 2023]
  • Hi Dollar,

    Thanks for reaching us. Please help us more about your application and use case. so that we can guide you better. For answering your question

    1. Yes, The A2B_CLK1CFG register enables an output clock on the A2B_ADR1, to drive the peripherals connected to it. CLK1INV (R/W) bit helps to invert the clock phase for improving the EMI performance.

    2. The maximum microphone support for our AD2428W transceiver is four. AD2428 has two DRX pin which can be configured as PDM interface for using microphone capability. Each DRX pin can accommodate two microphones by sampling at the rising and trailing edge of the clock pulse. This can be enabled by connecting the LR_SEL pin to VCC or GND. The data at two different DRX pin can be send to downstream or upstream. All four-microphone data will be sampled at the same time. which helps it give better in ANC and RNC applications.

    3. Super frame consists of SCF, SRF, Downstream and Upstream data. where SCF is generated by Main node, and it precedes the Downstream data. SRF is generated by last inline sub node, and it precedes the upstream data.



  • First of all, thank you very much for your answer.Regarding the third reply, I found that I did not describe it very clearly. I want to talk about the same node.Thank you!

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