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Category: Hardware
Product Number: SSM6515

Hi Team,

     I uses SSM6515 as  a headphone driver,but there is no output.The  situation is as follows

     1.IIC communication runs well,  VENDOR_ ID  DIVICE_ ID can be read normally, FAIL_ CTRL data read as 0x00.

     2.The IIS signal is set to  24-bit 48K 。Use oscilloscope measure the LRCLK frequency at 48k, BCK signal at 6.173MHz, and SCK signal at 12.25MHz.

     3.The configuration parameters of SSM6515 register are as follows

          CLK_CTRL:   0x00,Attempted 0x05


          DAC_CTRL2:   0x10              


          DAC_VOL:     0x03

          SPT_CTRL2:   0x22,Attempted  0x00

           AMP_CTRL:   0x14

           RESET:           0x10

Currently, using an oscilloscope to connect OUT_ P. OUT_ N No audio signal coming out.

Could you please help check if there are any issues with the register settings?  If there are any issues, please provide suggestions for register settings


  • Hi shanyx,

    I've attached a working SigmaStudio project that contains all the necessary register writes to help fix your issue


    I noticed a couple key takeaways from reading your register settings that may help you in the future:

    1. RESET = 0x10 means that the board is in a Full Reset state. This register needs to be 0x00. Not sure if these bits were toggled by a register setting script, but these bits should remain 0x00 if you want to output signal from the amplifier.

    2. DAC_VOL = 0x03 means that you were setting the volume to have an additional 22.875dB gain. If this was intentional, you can disregard this comment, but if not, this should at least be set to 0x40 to yield a 0dB gain if you are not seeing output from the amplifier to avoid clipping while troubleshooting I/O.

    3. Your BCLK rate should always be an integer multiple of your LRCLK rate to have a valid PCM format. With your LRCLK = 48kHz, and assuming you want I2S with 32-bit Slot Width with 24-bit data, using a 2CH setup yields a 3.072MHz BCLK rate or using a 4CH setup yields a 6.144MHz BCLK rate. (Number of Channels x LRCLK Rate x Slot Width = BCLK Rate).

    I made some assumptions in the SigmaStudio project that you desired 32 BCLK's per slot with 24-bit data along with an LRCLK rate of 48kHz, but was unsure if you were using 2 Channels or 4 Channels based on your oscilloscope readings of your BLCK at 6.173MHz. 

    If that is not correct, I'd be happy to make some further adjustments to your setup and help clear up any further issues.

    Hope the project helps clear up the issues you were experiencing!