The datasheet did not show how to configure the PLL/Clock for a 16kHz sampling frequency.
Rev. A | Page 13 of 44: It seems only sampling frequencies 32kHz and above are supported? Also Table 9 did not show settings for fs = 16kHz.
In Table 1 fs is specified from 8 kHz to 192kHz.
Question: How must be the PLL/Clock configured for fs = 16kHz?
Is there a simulation model available (VHDL, Spice, MATLAB, …)?