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ADAU1978 Production
The ADAU1978 incorporates four high performance, analog-to-digital converters (ADCs) with 2 V rms capable ac-coupled inputs. The ADCs use a multibit sigma...
Datasheet
ADAU1978 on Analog.com

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ADAU1978-PLL/Clock for fs = 16kHz, any kind of simulation model available

kfraus

on Aug 25, 2023

Category: Software

Product Number: ADAU1978

ADAU1978:

The datasheet did not show how to configure the PLL/Clock for a 16kHz sampling frequency.

Rev. A | Page 13 of 44: It seems only sampling frequencies 32kHz and above are supported? Also Table 9 did not show settings for fs = 16kHz.

In Table 1 fs is specified from 8 kHz to 192kHz.

Question: How must be the PLL/Clock configured for fs = 16kHz?

Is there a simulation model available (VHDL, Spice, MATLAB, …)?

0 galvinpjg

on Sep 21, 2023 11:40 AM

Kfraus,

Please see the table below. 16kHz is indeed supported, so long as the PLL is in MCLK mode. The 32kHz restriction is applicable if the PLL is in LRCLK Mode. But MCLK mode for PLL should work with 16kHz.

If FS = 16kHz, then the FS bits should be set to b001. From there, the MCS bits will be set accoridng to the frequency of MCLK. If MCLK = 8.192MHz for example, then MCLK:LRCLK ratio = 512. Hence the MCS bits should be set for "512" in the "16-24kHz" row of the table. This means MCS bits = b001.

FS: Bits [2:0] of Register Address 0x05	MCS: Bits [2:0] of Register Address 0x01
	000	001	010	011	100
	MCLK:LRCLK Ratio
[000] / 8 - 12 kHz	512	1024	1536	2048	3072
[001] / 16- 24 kHz	256	512	768	1024	1536
[010] / 32- 48 kHz	128	256	384	512	768
[011] / 64 - 96 kHz	64	128	192	256	384
[100] / 128 - 192 kHz	32	64	96	128	192


Note: This table assumes a minimum of 2 channels.

Please let us know if there are additional questions.

Thanks,
PG

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ADAU1978-PLL/Clock for fs = 16kHz, any kind of simulation model available