AD1938 voltage range

Hi teli ,

I have moved this thread here (+) Q&A - Audio - EngineerZone (analog.com). Someone from the community should be able to assist you.

Regards,

JC

Hello Teli,

Sorry for the delay. I have been on an extended business travel trip and upon my return there was a company-wide shutdown. 

You did come up with the correct numbers but not quite by the theoretical correct way to calculate them.

The 1.9V RMS is a differential number so this is with the ADC being driven differentially so we are looking at two pins not one. Each pin is being driven with half the signal level. The "full scale" input voltage for one pin will be half that so it will be 0.95Vrms. I put the "full scale" in quotes because only driving one pin you will not be able to drive the pin to actual 0dBFS. You can only go up to -6dBFS. This would be the case if you held one input steady at the CM voltage and only drove one pin. 

"full scale"(-6dBFS) = 0.95Vrms. This translates to 2.6866Vpp. ( 0.95 x 2.828 ) 

This voltage will swing 2.6866/2 = 1.3433Vp above and below the 1.5V CM voltage. 

There is some headroom in the analog design so you may be able to go a little higher than -6dBFS but then you get into the higher THD and will clip eventually and these higher THD and clipping points will differ from part to part and over temperatures etc. This is why we specify it at this level where we can guarantee the performance over temperatures and silicon skews. It will clip before you reach 0dBFS so if you need full resolution you will have to drive it differential. 

The differential numbers are calculated in a similar way. 1.9Vrms x 2.828 = 5.3732Vpp. This does not exceed the max voltage on the pins because each pin is only seeing half the voltage. 

If you are planning to use two of the DACs as a differential pair, then the same calculations will apply. You can get twice the output differentially than you will single ended. 

Also note that if you put in a certain level into the ADC, pick a level,... 1Vrms. Then jumper the ASDATA over to the DSDATA and invert one channel etc., you will not get 1Vrms out of the DAC. Full scale output voltage is 0.88Vrms. It is a little less than the 0.95Vrms of the ADC single ended. I wish this were not the case but the designers had their reasons. 

I also should point out that if you want to see the differential performance of the DACs if you use two of them you can refer to the AD1937 datasheet and that will give you an idea of what to expect.

teli said:

I understand that some specification ( DC spec , linearity, how to use and so on) is different from regular ADCs and DAC.

If you are looking at other architectures like SAR ADCs and R2R DACs then yes, many of the measurement specifications do not really apply since these converters use Sigma-Delta modulation. Where you may run into problems is if you are measuring DC or very low frequencies the resolution will be poorer and there may be a little more drift over time and temperature. If your application is very sensitive to errors at DC or close to it then it might be a problem. Higher frequencies are usually not a problem and the fact that they are oversampling makes the requirements for the anti-alias filter to be easier to meet and a simpler design. The other possible issue might be idle tones if the noise floor is very low and the signal is very small. There are ways to remove the idle tones but that is another topic. 

Dave T