ADAU1467 MFxLMS training procedure question

Hello TK,

Thanks for the well detailed post and the project file. This will need a little more study on my part. 

I did just take a quick look at your project and one thing stood out. 

You did setup clock generator 1 to have the X1 output be an 8kHz fs. So that was properly setup assuming you are using a 12.288MHz master clock input. 

In your project you are using serial input port 3, channels 40 and 41. In the register settings you have that serial port setup for a X1 rate of 193kHz and then you are using the /3 setting which will give you a 64kHz sampling rate. So that is what should be coming out of the serial port to go to the 1777. The DSP core start pulse is set to use clock generator 1 nominal X1 output so the core is running at 8kHz but the serial input port is running at 64kHz. So it is picking up 8 samples for every one that the core actually picks up. So seven samples are thrown away every frame. 

for the serial output ports you are using port 3 and it is also running at the 64kHz rate. So this means that every sample the core produces is being output eight times. The other strange thing is that you are using output ports numbers 44 and 45. Those are in the middle of the eight possible channels for this port. You have the port setup for two channel operation. These are the first two channels of the second half of the frame and with a 50/50 duty cycle. You should not be seeing any data out of this part or if the LTCLK polarity is flipped it might work because of it being the second half of the frame. 

You are somewhat negating the low latency of the 1777 by running things this low. If you were to setup the serial ports to run at 8kHz then it will take a LONG time for the data to be transmitted and the ASRC will also take some time. I really do not see a reason for running the sigmaDSP core at 8kHz. I would run it at 48kHz or maybe even 96kHz and that would make the transmission time less and the ASRC would have less latency and the conversion should be faster. Right now I think you have so much distortion from all the zero order holds going on with the serial ports that it is getting in the way of the filter conversion. 

By the way, I also see you are basically using the 1777 as a codec and not doing the ANC there. I guess this is fine and you put some filters there. That is good. 

These are my initial thoughts...

Dave T

Hi Dave,

thank you for the fast reply and initial guidance! 

Actually the external master input clock is 3.072MHz (provided by the ADAU1777).  But I assumed this would give me a 8kHz fs according to my clock register settings: 

=>  3.702MHz  /1  x96  /1024  x1/36  =  8kHz  at CLK Gen1 output.  Please let me know if my settings are not correct.

My plan was to run the 1467 core fs at 8kHz to get a better frequency resolution (8kHz/256 filter length).  This way I wouldn’t need to up and down convert in the dsp core.  And then have the output restructure filter in the 1777 take care of the resulting distortion. My input and output serial rate was still planned to be 192kHz.

I do realize now that my serial clock settings are not correct.  I will start making your suggested changes when I’m back in the office and will let you know my results.

Thanks again!

TK