AD1938 CODEC Full-Scale Input Voltage (Differential)

Hello Mahendrakumar,

Note that the specification is differential. 1.9Vrms. So this is 5.37Vp-p. But this is between two pins.

The pins sit at a common mode voltage of roughly 1.5V. So one pin needs to swing a total of 2.69 V for full scale input.

So this is 1.34V above and below the 1.5V. So the max will be 1.5V + 1.34V = 2.84V and 1.5V - 1.34V= 0.16V So this is the full swing of each pin. 

So since one pin will be full positive and the other pin full negative you get the full swing of 5.37V difference between the pins. Each pin individually is within the 3.3V and ground but the difference of the two will be greater. 

I know it is a bit tricky to see. Look at it on a scope and you can see this in action. 

You question about the power supplies. The AD1938 eval board was designed to have a lot more headroom and to be able to have more gain if desired. One was designed more for pro audio applications and the other for a lower cost solution suitable for most consumer applications. No huge secret here, just personal preference and applications needs.

Dave T

Hi Dave

I am replicating the AD1938 CODEC to my PCB. I am referring to the circuits from the UG-045 AD1938 eval board document. But I am not sure what these circuits are for. please help me understand what the circuit below does?

1) what this opamp circuit does before the audio input from the 3.5mm aux connector is fed to the CODEC ADC inputs?

2) why is the +12V and -12V power supply needed for the opamp(OP275)? can I just have a single 5V supply? If I just have a single positive supply what are the limitations I will have on the audio quality compared to  +12V to -12V opamp supply?

Appreciate your support!

Thanks

Santosh

Hi Dave

Thank you. I did a ltspice simulation and the confusion about signal waveform is clear now.

1) Should I have two GND planes Analog and Digital Ground for this CODEC on my PCB?

or a single GND plane is ok?

2) What should be the trace impedance for the ADC differential inputs? 50ohms single-ended or 100ohm differential?

Hi Dave 

any update on the above queries?

1) Should I have two GND planes Analog and Digital Ground for this CODEC on my PCB?

or a single GND plane ok?

2) What should be the trace impedance for the ADC differential inputs? 50ohms single-ended or 100ohm differential?

3) what to do with unused ADC inputs and DAC outputs? how to terminate them?

Thanks

Santosh

Hello Santosh,

One ground plane is best. Look at the ADAU1452 datasheet for how to layout bypass caps properly between the pins and the vias to the ground and power planes. 

For the AD1938 you should not put a ground plane on the top layer under the part that is connected to ground pins on the part. You can have a plane on the top layer but keep the pins from connecting to it. It is important for the ground pins to have only one trace go from the pin to the bypass CAP then to the ground plane on the top and vias to the ground plane. Keep all the bypass caps on the same side of the PCB that the codec is on. Keep the Loop Filter parts on the same side as the part and connections to the part short. 

Trace impedance for the ADC is not super important. It is good to make them the same. 75 or 50 ohms seems like a good number. Like I said, we do not specify anything specific. 

Unused ADCs, You should either tie them to the CM pin or you can tie them to ground through a cap. A 1uf to 10uf would be fine. Most of the time people will tie them to the CM pin for cost reasons. 

Unused DACs. These can be left floating with no connection. If you need to terminate all pins then use a 10K to ground. 

Dave T

Hi Dave

We need clarification on AD1938 MCLK Clock scheme.

Path 1: Host processor will feed the MCLK to CODEC.

Path 2: 12.288MHZ Oscillator will feed MCLK to Host processor and CODEC.

Please verify the MCLK Clock scheme is correct. Also clarify the below queries.

Queries:

1. We are implementing two clock paths as shown in the image on our board (TDM implementation) are these connections Path1 and Path2 valid?
2. What is the purpose and use of MCLKO pin ?
3. Can we make the MCLKO pin as “NO CONNECT” When the clock feed from path 1 or path 2?

Regards

R.Mahendra kumar

Hello R. Mahendra Kumar,

To get the best performance you need to use a low jitter clock. It is often not the best to get it from a host processor if it can be avoided. So I would opt for path 2 for sure. 

The MCLKO pin is actually a multi-use pin. If you use a crystal then you will need to set this pin to the crystal oscillator output function to allow a crystal to oscillate. 

If you use a clock oscillator module, or some other clock source, then you can program this to be a clock output that is after the internal PLL. This allows you to use the PLL to provide a cleaner clock to the rest of the design. 

If you are not going to use it for either use then you can shut it off. So yes, do not connect anything to the pin and shut it off in the register settings. 

You have not discussed the frame clock (LRCLK) and bit clocks. I recommend you use the ADC LRCLK and BCLK outputs to drive the host processor. This way you use the internal PLL to run the ADC and then slave the host off of that. The ADC is the most susceptible to jitter so this will produce the bast performance. 

When you start the PCB layout check the forum. I have commented on the layout for these parts several times and there are some important things to do to prevent problems. 

Dave T

Hi Dave

• I have attached the signal path for LRCLK and BCLK also. Please verify this and provide your suggestions.
• Also please share the links for suggested layout guidelines for AD1938.

Regards

R.Mahendra kumar

Hi Dave

Is there any update on above Query?

Regards

R.Mahendra kumar

Hello R.Mahendra, 

This is what I suggest.

What sample rate do you intend to use?

What TDM format? ( how many channels) It looks like you plan to use TDM8?

Look at the PCB design considerations section of the ADAU1452 datasheet. The newest revision that I did back in 2018? 

Then the other detail is not to connect the pad under the device to anything except a bunch of vias to the ground plane. Do NOT tie it to any of the ground pins of the part. Let those go past a capacitor then to ground on their own vias. You will have to keep the ground plane on the top from filling into the pain and the EP on the bottom of the part. Do not let them connect. 

ALL of the decoupling caps must be on the top of the PCB and connected like the ADAU1452 datasheet shows. . 

Dave T

Hi Dave

We are using 8k, 16k, 32k, 48k, 96khz sampling rates and TDM8 format.

Also, we are planning to use AD1938 CODEC to test our Host processor (DUT) TDM interface.

From the above diagram, please confirm the below points.

1. To connect CODEC mclko to rx mck is to ensure that the interfaces are synchronous to each other, or is there some other explanation?
2. In this, what happens to the txmck from host?
   For synchronous behavior, we think that the tx mck also has to be provided from the mcko, just like rx mck.
3. Rx_fsync – Alrclk, Rx_sck – Abclk, connections would be bidirectional, as per master / slave configuration, right?

Regards

R.Mahendra kumar

Hello R.Mahendra kumar,

Mahendrakumar said:

To connect CODEC mclko to rx mck is to ensure that the interfaces are synchronous to each other, or is there some other explanation?

Yes, to make them synchronous. 

Mahendrakumar said:

In this, what happens to the txmck from host?

You do not use it. No, you do not need to use the txMCK unless that processor is not capable of using an external clock. It seems to be it can but I do not know that part. I am just advising you of the best way to do clocking with the least amount of jitter. 

Mahendrakumar said:

Rx_fsync – Alrclk, Rx_sck – Abclk, connections would be bidirectional, as per master / slave configuration, right?

The pins on the codec are bi-directional but the directions I showed should be followed. This will give you the best timing margin for the data transmission and to be able to run at the higher sample rates. You are asking me what is the best way and this is the best way. 

Dave T

Hello R.Mahendra kumar,

Mahendrakumar said:

To connect CODEC mclko to rx mck is to ensure that the interfaces are synchronous to each other, or is there some other explanation?

Yes, to make them synchronous. 

Mahendrakumar said:

In this, what happens to the txmck from host?

You do not use it. No, you do not need to use the txMCK unless that processor is not capable of using an external clock. It seems to be it can but I do not know that part. I am just advising you of the best way to do clocking with the least amount of jitter. 

Mahendrakumar said:

Rx_fsync – Alrclk, Rx_sck – Abclk, connections would be bidirectional, as per master / slave configuration, right?

The pins on the codec are bi-directional but the directions I showed should be followed. This will give you the best timing margin for the data transmission and to be able to run at the higher sample rates. You are asking me what is the best way and this is the best way. 

Dave T